Synchronous Memory Read Clock Start-Stop Control
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Solution Overview
Problem
Existing DDR DRAM technologies, while improving data transmission speed, lack flexibility and efficiency in managing the read clock signal, leading to increased power consumption and design complexity in high-performance applications like graphics processing units (GPUs).
Innovation Solution
A memory system with a read clock circuit and mode register that allows programmable control of the read clock signal, enabling modes such as 'read-only', 'always-on', and 'disabled' to optimize power usage and simplify memory controller design by allowing the read clock to start and stop based on command types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the read clock signal is continuously provided to maintain synchronization, then signal integrity and timing accuracy are improved, but power consumption increases
Solution Approach 1:
The read clock signal transitions from continuous operation to periodic operation, where the clock is activated only during read operations and deactivated during write operations or idle periods. This periodic activation maintains signal integrity when needed while significantly reducing power consumption during infrequent read operations, directly resolving the technical contradiction between reliability and energy usage.
2Reliability
If the read clock signal is continuously provided to maintain synchronization, then timing accuracy is improved, but device complexity increases
Solution Approach 1:
The memory controller implements dynamic clock management where the read clock signal's activation and deactivation are automatically controlled based on the type of operation being performed. This dynamic approach eliminates the need for complex interamble calculations and manual timing adjustments, reducing device complexity while maintaining timing accuracy through automated synchronization control.
3Use of energy by moving object
If the read clock is programmed to start and stop based on command types, then power efficiency is improved, but device complexity increases
Solution Approach 1:
The memory controller implements self-service clock management where the system automatically determines when to activate or deactivate the read clock based on the command type received from the host processor. This self-service mechanism eliminates the need for external complex control logic, as the memory controller autonomously manages clock timing based on its internal command decoding, thereby improving power efficiency without proportionally increasing device complexity.
Data Source
AI summary
A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.