Synchronous Microprocessor Testing via Dynamic TAP Mode Switching
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Solution Overview
Problem
Maintaining synchronization between a gold microprocessor and a device under test (DUT) during microprocessor testing is challenging, and efficiently comparing their internal states to detect differences is difficult, as disturbances can invalidate data comparisons.
Innovation Solution
A system with a gold processor, a test access port (TAP), and an interface control unit that operates in multiple modes to ensure synchronous functional lockstep between the gold processor and DUT, allowing simultaneous or exclusive provision of test signals, and independent access to test output data through dedicated connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single TAP is shared between gold processor and DUT, then device complexity is reduced, but synchronization reliability deteriorates due to difficulty in maintaining synchronous functional lockstep
Solution Approach 1:
The system dynamically switches between different operational modes (first mode for simultaneous testing, second mode for gold processor only, third mode for DUT only) based on test requirements. The interface control unit dynamically controls the switch to route TAP signals to appropriate processors, enabling flexible adaptation while maintaining synchronization reliability when needed.
Solution Approach 2:
The single TAP is designed to serve multiple functions by being shared between gold processor and DUT through the switch mechanism. It can provide test signals to both processors simultaneously or exclusively to one processor depending on the operational mode, reducing overall system complexity while maintaining testing capability.
2Productivity
If test signals are provided to both gold processor and DUT simultaneously, then testing efficiency is improved, but synchronization difficulty increases
Solution Approach 1:
The interface control unit acts as an intermediary between the TAP and the processors, intelligently routing test signals to maintain synchronous functional lockstep between gold processor and DUT. It coordinates the simultaneous provision of test signals while managing the complexity of synchronization, making the system easier to operate.
Solution Approach 2:
The system can dynamically switch between providing test signals to both processors simultaneously (first mode) or exclusively to one processor (second or third modes), allowing optimization between testing efficiency and synchronization ease based on specific test requirements.
3Measurement precision
If internal state observation is performed without disturbance, then measurement precision is improved, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The interface control unit serves as an intermediary that manages access to processor internal states through the TAP. It controls the observation process to prevent disturbances while coordinating between gold processor and DUT, achieving precise measurement without requiring complex additional control mechanisms at the processor level.
Solution Approach 2:
The processors themselves provide their internal state information through the TAP interface when controlled appropriately. The system leverages the processors' own test interfaces to enable observation, reducing the need for external disturbance-free observation mechanisms.
4Productivity
If data comparison is performed quickly between gold processor and DUT, then productivity is improved, but measurement precision may deteriorate due to rushed comparison processes
Solution Approach 1:
The system prepares test data and comparison mechanisms in advance during the testing process. By maintaining synchronous functional lockstep and pre-coordinating test signal provision, the comparison process can proceed quickly without sacrificing precision, as the groundwork is already laid for accurate difference detection.
Solution Approach 2:
The interface control unit acts as a mediator that coordinates efficient data comparison between gold processor and DUT. It manages the comparison process to ensure both speed and accuracy by properly timing and routing data flows, preventing rushed comparisons that would compromise precision.
Data Source
AI summary
A system for testing a processor. The system includes a gold processor and a test access port (TAP). A processor that is a device under test (DUT) is coupled to both the gold processor and the TAP. In the first mode, the TAP provides test signals to both the gold processor and the DUT while they operate in synchronous functional lockstep. In the second mode, the TAP provides signals to the gold processor. In the third mode, the TAP provides test signals to the DUT. A host computer coupled to the interface control unit executes a software application to cause the TAP to drive test signals and to access test output data from the gold processor and the DUT. Test output data accessed from the gold processor may be compared to that accessed from the DUT to determine any differences. The comparison data generated may then be used for further analysis.