Synchronous PCS Datapath with Elastic Buffers for Deterministic Latency
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Solution Overview
Problem
Existing programmable logic devices (PLDs) face challenges in achieving deterministic latency in their datapath architectures, particularly due to clock domain crossings and variations in clock rates, which affect the predictability and efficiency of data transmission.
Innovation Solution
The implementation of a fully synchronous datapath architecture for the physical coding sublayer (PCS) with elastic buffers that operate according to identical read and write clocks, and the use of gearboxes devoid of clock domain crossings, ensures deterministic latency by mitigating clock skew and allowing for precise latency monitoring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clock domain crossings are used in datapath architecture, then adaptability to different clock rates is improved, but latency determinism deteriorates
Solution Approach 1:
The patent extracts and eliminates clock domain crossings from the datapath architecture. By removing the clock domain crossing infrastructure and instead using a fully synchronous architecture where all flip-flops are clocked by the same clock signal, the system achieves deterministic latency while maintaining adaptability through configuration options for different data rates and formats.
Solution Approach 2:
Instead of adapting to different clock rates through clock domain crossings (the conventional approach), the patent inverts the approach by using a single synchronous clock and adapting the data path width and timing instead. This inversion allows precise latency control while maintaining flexibility for different protocols and data rates.
2Adaptability or versatility
If elastic buffers with different read and write clocks are used, then adaptability to clock variations is improved, but latency prediction accuracy deteriorates
Solution Approach 1:
The patent removes the dual-clock elastic buffer architecture and replaces it with single-clock synchronous buffers. This extraction of the clock domain crossing mechanism eliminates the source of latency variation, allowing precise latency prediction while maintaining adaptability through configurable data paths and rate matching at the protocol level.
Solution Approach 2:
The patent changes the operational parameters by using identical clock frequencies for all synchronous elements. Adaptability to different data rates is achieved not through clock frequency variation but through configurable buffer depths, data path widths, and protocol-specific timing parameters, all under a unified clock domain.
3Loss of time
If fully synchronous datapath architecture is implemented, then latency determinism is improved, but device complexity increases
Solution Approach 1:
The patent merges all clock domains into a single synchronous clock domain, eliminating the need for separate clock management circuits, phase alignment logic, and domain crossing synchronization. This consolidation reduces overall system complexity while achieving deterministic latency through uniform timing across all datapath elements.
Solution Approach 2:
The patent segments the adaptability requirements into separate configurable parameters (buffer depth, data path width, protocol mode) rather than requiring complex clock domain infrastructure. This segmentation allows the synchronous architecture to handle different protocols and rates through parameter configuration rather than structural complexity.
Data Source
AI summary
Various techniques are provided to implement physical coding sublayer (PCS) datapath systems and methods with deterministic latency. In one example, a PCS circuit includes an elastic buffer configured to operate according to a read clock associated with a read domain and a write clock associated with a write domain. The elastic buffer is configured to generate a first signal associated with the write domain and indicative of a first difference between a read pointer and a write pointer. The elastic buffer is further configured to generate a second signal associated with the read domain and indicative of a second difference between the read pointer and the write pointer. The PCS circuit further comprises a logic circuit configured to determine a phase difference between the read clock and the write clock based on the first signal and the second signal. Related methods and systems are provided.