Insulated Synchronous Rectification DC/DC Converter Fault Detection
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Solution Overview
Problem
The secondary-side controller in insulated synchronous rectification DC/DC converters is prone to abnormal operations due to inaccurate control time measurement caused by short circuits or open circuits in the SET terminal, leading to unreliable operation of the synchronous rectification transistor.
Innovation Solution
A secondary-side controller with an abnormal state detection circuit that can detect open-circuit and short-circuit states in the SET terminal, asserting a detection signal to suspend the switching operation of the switching transistor and incorporating a fail circuit to prevent false detections, thereby ensuring reliable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the SET terminal is used to measure control time for synchronous rectification transistor operation, then the operation timing can be controlled, but short circuits or open circuits in the SET terminal cause inaccurate measurement leading to abnormal operations
Solution Approach 1:
The patent applies preliminary action by detecting abnormal states (short circuits or open circuits) in the SET terminal before they cause inaccurate control time measurement and abnormal transistor operation. The detection circuit proactively identifies faults in the external resistor or capacitor connected to the SET terminal, allowing the system to prevent erroneous operation timing before it occurs.
Solution Approach 2:
The patent implements feedback by using a detection circuit that continuously monitors the state of the SET terminal and provides feedback information about abnormal conditions. When the detection circuit identifies a short circuit or open circuit, it generates a detection signal that feeds back to the control system, enabling the system to respond to and correct the abnormal state, thereby maintaining reliable operation.
2Productivity
If the synchronous rectification transistor is controlled based on measured control time, then rectification timing can be optimized, but faults in the SET terminal lead to false detections and unreliable operation
Solution Approach 1:
The patent applies preliminary action by detecting abnormal states (short circuits or open circuits) in the SET terminal before they cause inaccurate control time measurement and abnormal transistor operation. The detection circuit proactively identifies faults in the external resistor or capacitor connected to the SET terminal, allowing the system to prevent erroneous operation timing before it occurs.
Solution Approach 2:
The patent implements feedback by using a detection circuit that continuously monitors the state of the SET terminal and provides feedback information about abnormal conditions. When the detection circuit identifies a short circuit or open circuit, it generates a detection signal that feeds back to the control system, enabling the system to respond to and correct the abnormal state, thereby maintaining reliable operation.
Data Source
AI summary
An external circuit element RSET is connected in use to an SET terminal. A synchronous rectification controller generates a pulse signal S1 based on a control time determined according to the state of the SET terminal. A driver switches on and off the synchronous rectification transistor according to the pulse signal S1. An abnormal state detection circuit is capable of detecting an open-circuit state and/or a short-circuit state that can occur in the SET terminal. When the abnormal state detection circuit detects such an open-circuit state and/or short-circuit state, the abnormal state detection circuit asserts a detection signal S11. When the detection signal S11 is asserted, a primary-side controller arranged on the primary side of the DC/DC converter is instructed to suspend the switching operation of a switching transistor.