Synchronous Rectifier Control Circuit for DC-DC Converter Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Synchronous rectification type DC-DC converters face efficiency reduction when the load is small due to inaccuracies in detecting reverse coil currents and offset timing, leading to increased energy loss and reduced conversion efficiency.
Innovation Solution
A control circuit that includes a detection circuit to compare a reference voltage with the voltage at a node between the main and synchronization switches, generating a control signal to regulate the switching timing of the synchronization switch, thereby optimizing its inactivation timing and reducing energy loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If reverse flow detection is used to control synchronization transistor inactivation, then conversion efficiency is improved, but measurement precision deteriorates due to process variations affecting detection accuracy
Solution Approach 1:
The patent replaces the mechanical/electrical reverse flow detection method with a voltage-based detection method. Instead of detecting the actual reverse current flow through the coil, the system detects the voltage at the node between the main transistor and synchronization transistor, which indicates the coil current state. This substitution eliminates the accuracy problems caused by process variations in reverse flow detection while maintaining the ability to control synchronization transistor inactivation timing.
Solution Approach 2:
The patent introduces an intermediary voltage signal as a mediator to indicate the coil current state. Rather than directly detecting the coil current or its reverse flow, the system uses the voltage at the node between transistors as an intermediary indicator. This voltage reflects the charging state of the coil and allows indirect but accurate detection of when the coil current reaches zero, enabling precise synchronization transistor control without direct reverse flow detection.
2Stability of the object's composition
If capacitor charging and discharging are balanced with one-shot pulses, then switching timing is stabilized, but offset period is introduced that reduces reverse flow detection accuracy
Solution Approach 1:
The patent extracts and eliminates the offset period caused by capacitor charging/discharging balancing. Instead of using one-shot pulses to balance capacitor charges (which creates timing offsets), the system directly uses the voltage detection method to determine synchronization transistor inactivation timing. This removes the intermediary balancing step that introduced the offset, allowing accurate detection of coil current zero-crossing points without timing errors.
3Reliability
If synchronization transistor remains activated during small load, then output voltage is maintained, but energy loss increases due to current flowing from load to ground
Solution Approach 1:
The patent implements dynamic control of the synchronization transistor activation period based on real-time voltage detection. Instead of maintaining a fixed activation period, the system dynamically adjusts the inactivation timing by detecting when the voltage at the node indicates zero coil current. This dynamic adjustment allows the transistor to remain activated only as long as needed to maintain output voltage, and is inactivated promptly when the coil current reaches zero, preventing unnecessary energy loss during small load conditions.
Data Source
AI summary
A control circuit for controlling a power supply including a first switch and a second switch coupled in series between a first potential and a second potential. The control circuit includes a detection circuit that detects a magnitude relation of a voltage value at a node between the first and second switches and a reference value during a period in which the first switch and the second switch are inactivated. The detection circuit generates a control signal corresponding to the magnitude relation. A regulation circuit regulates a switching timing of the second switch in response to the control signal to decrease a difference between the voltage value at the node and the reference value.


