Synchronous Rectifier Gate Timing for Low-Loss Wireless Power
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Solution Overview
Problem
Current wireless power transfer systems face limitations in power transfer efficiency and alignment requirements due to the reliance on magnetic and electric field coupling, with inefficiencies in rectification processes, particularly in resonant systems, and the use of lossy diodes.
Innovation Solution
A synchronous rectifier using a field effect transistor (FET) with a gate signal in phase with the input signal, driven by a trigger circuit that synchronizes the gate signal with the input signal, and an input stage for optimizing load impedance and reducing harmonics, enabling efficient power transfer via electric or magnetic field coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If resonant magnetic systems or resonant electric field systems are used to increase power transfer range and rectify alignment issues, then power transfer range is improved, but rectification inefficiency and energy loss occur due to the use of lossy diodes
Solution Approach 1:
The patent changes the rectification mechanism from passive diode-based rectification to active synchronous rectification using FETs controlled by gate signals. This parameter change in the rectification approach eliminates the forward voltage drop losses inherent in diode-based systems, thereby reducing energy loss while maintaining the extended power transfer range enabled by resonant coupling.
Solution Approach 2:
The patent substitutes the mechanical/passive diode rectification system with an electronically controlled FET-based synchronous rectification system. This substitution allows for more efficient power conversion by using electronically controlled switches that can be timed to minimize losses, replacing the inherently lossy diode mechanism while preserving the benefits of resonant field coupling for extended range.
2Loss of energy
If synchronous rectification with FET and gate signal in phase with input signal is implemented, then power transfer efficiency is improved, but device complexity increases due to trigger circuit and gate signal synchronization requirements
Solution Approach 1:
The patent implements feedback mechanisms where the trigger circuit monitors the input signal and generates appropriately timed gate signals for the FETs. This feedback-based synchronization ensures that the FETs switch at optimal moments to maximize rectification efficiency, and the same feedback infrastructure can be used for control and diagnostics, helping to manage the increased complexity through intelligent control rather than additional passive components.
Solution Approach 2:
The trigger circuit and control system serve multiple functions: generating gate signals for synchronous rectification, providing synchronization reference, enabling efficiency monitoring, and supporting system control. By making the control infrastructure multi-functional, the patent reduces the need for separate dedicated circuits for each function, thereby managing overall device complexity while achieving high power transfer efficiency.
3Reliability
If input stage for optimizing load impedance and reducing harmonics is added, then power transfer stability and efficiency are improved, but device complexity increases
Solution Approach 1:
The patent merges the impedance optimization and harmonic reduction functions into a single integrated input stage that works in conjunction with the synchronous rectification circuit. By combining these functions rather than adding separate dedicated circuits for each, the patent achieves improved power transfer stability and efficiency while minimizing the increase in overall device complexity through functional integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances power transfer efficiency and stability by ensuring sinusoidal current input and reducing harmonic content, maintaining efficiency from no-load to full-load conditions, and providing a stable rectified voltage, thus improving overall system performance.
Implementation Method 1
a synchronous rectifier using a field effect transistor (FET) with a gate signal in phase with the input signal, driven by a trigger circuit that synchronizes the gate signal with the input signal
Implementation Method 2
driven by a trigger circuit that synchronizes the gate signal with the input signal
Implementation Method 3
an input stage for optimizing load impedance and reducing harmonics
Implementation Method 4
ensuring sinusoidal current input and reducing harmonic content
Implementation Method 5
power transfer occurs due to coupling of electric fields between the capacitive electrodes of the transmit and receive elements
Implementation Method 6
Power transfer occurs due to coupling of magnetic fields between the induction coils of the transmit and receive elements
Implementation Method 7
Resonant magnetic systems, which transfer power due to coupling of magnetic fields between the induction coils of the transmit and receive elements also exist
Data Source
AI summary
A rectifier for use in a receiver of a wireless power transfer system for receiving wireless power transferred for a transmitter of the wireless power transfer system. The rectifier comprises a field effect transistor (FET) comprising: a source terminal electrically connected to ground; a drain terminal electrically connected to a receive element of the receiver. The receive element is for extracting power from the transmitter of the wireless power transfer system. The FET further comprises a gate terminal electrically connected to the receive element. The gate terminal is driven by a gate signal in phase with an input signal received at the receive element.