Synchronous Rectifier Turn-Off via Primary Switch Spike Detection
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Solution Overview
Problem
In flyback converters during continuous conduction mode, the simultaneous on-time of primary-side and secondary-side transistors leads to power wastage and potential component damage due to the high slew rates of winding currents, as conventional methods for switching off the synchronous rectifier transistor are delayed, causing energy loss and exceeding current ratings.
Innovation Solution
A spike detector is introduced on the secondary-side to detect voltage spikes indicative of the primary transistor's turn-on, allowing the synchronous rectifier controller to switch off the SR transistor more quickly, thereby reducing or eliminating simultaneous on-time and preventing excessive currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional VDS threshold detection is used to turn off the SR transistor, then the control method is simple, but the SR transistor turns off delayed causing simultaneous on-time with PS transistor leading to power loss and potential component damage
Solution Approach 1:
The patent introduces a current sensor as an intermediary component to detect the secondary winding current ISEC. This sensor provides accurate current information to the controller, enabling timely turn-off of the SR transistor before simultaneous conduction occurs, thereby reducing power loss without requiring complex control logic
Solution Approach 2:
The patent implements a feedback mechanism where the controller continuously monitors the secondary winding current ISEC through the current sensor and adjusts the SR transistor switching accordingly. This real-time feedback enables precise control to eliminate simultaneous on-time while maintaining simple control circuit architecture
2Reliability
If the SR transistor is kept on during CCM operation to maintain continuous conduction, then the output voltage regulation is maintained, but the high slew rate of winding currents causes excessive currents that may damage components
Solution Approach 1:
The patent applies preliminary action by detecting the secondary winding current ISEC in advance and using this information to proactively turn off the SR transistor before the high slew rate conditions occur. This preventive approach eliminates excessive currents and potential component damage while maintaining reliable operation
3Use of energy by moving object
If the leakage inductances are made significantly smaller than the magnetizing inductance to improve energy transfer, then the magnetic efficiency is improved, but the slew rate of winding currents increases causing delayed SR turn-off and simultaneous on-time
Solution Approach 1:
The patent replaces the conventional voltage-based detection method with a current-based detection system. By using a current sensor to monitor ISEC directly, the system can accurately detect current changes regardless of the slew rate, enabling timely SR transistor turn-off even when leakage inductances are minimized for improved energy transfer efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances efficiency by reducing power losses and preventing component damage by ensuring timely switching off of the SR transistor, thus improving the reliability and performance of flyback converters.
Implementation Method 1
the spike detector is in signal communication with an output capacitor (Cout) on the secondary-side and is configured to detect a voltage spike of an output voltage (VOut) across the output capacitor (Cout) that is indicative of the PS transistor being turned-on
Data Source
AI summary
A system for turning off a synchronous rectifier (SR) based on a primary switch (PS) turn-on detection in a flyback converter having a primary-side and a secondary-side is disclosed. The system comprises the PS on the primary-side, the SR on the secondary-side, a spike detector, and a SR controller. The SR is configured to produce a drain-to-source voltage (VDS). The spike detector is in signal communication with an output capacitor (Cout) on the secondary-side and the spike detector is configured to detect a voltage spike of an output voltage (VOut) across the Cout that is indicative of the PS being turned-on. The SR controller is in signal communication with the SR and the spike detector and the SR controller is configured to turn-off the SR based on the spike detector detecting the voltage spike of the VOut.