Synchronous Reset Pulse Across Multiple Clock Domains
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Solution Overview
Problem
Resetting circuitry across multiple clock domains is challenging due to independent clock frequencies and cycle requirements, making it difficult to determine when all domains have completed resetting, and asynchronous resets may fail to meet timing requirements, leading to incomplete or lost reset operations.
Innovation Solution
A method using an input synchronous reset pulse that is synchronized to a clock domain, held for a specified number of cycles, and then synchronized between domains to ensure coordinated reset completion, with monitoring for rising edges to confirm completion in each domain before clearing the reset pulse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an asynchronous reset pulse is transmitted to multiple clock domains, then all circuitry can be reset, but the reset pulse may not meet recovery and removal timing requirements in one or more clock domains
Solution Approach 1:
The patent changes the timing parameters of the reset pulse by synchronizing it to each clock domain's frequency. The reset pulse is held for a predetermined number of clock cycles in each domain, adjusting its duration and timing to meet the specific recovery and removal requirements of each clock domain rather than using a fixed asynchronous pulse width.
Solution Approach 2:
The patent introduces a synchronizer circuit as an intermediary between the asynchronous reset source and the multiple clock domains. This synchronizer captures the asynchronous reset pulse and regenerates it synchronized to each clock domain, acting as a mediator that adapts the reset signal to meet the timing requirements of different domains.
2Manufacturing precision
If independent reset pulses are used for each clock domain, then timing requirements can be met, but it becomes difficult to determine when all circuitry has completed resetting
Solution Approach 1:
The patent implements feedback by having each clock domain's synchronizer signal its reset completion status back to a central controller. The controller monitors these status signals and only clears the reset pulse when all domains have completed their reset operations, providing feedback information about the overall reset completion state.
Solution Approach 2:
The patent uses a universal reset completion signal mechanism that works across all clock domains. Each domain contributes its completion status to a common state, and the system provides a unified indication of overall reset completion, making the status tracking applicable to any number of clock domains.
3Reliability
If the reset pulse is held for several clock cycles in each domain, then all circuitry is properly reset, but the reset operation takes longer to complete
Solution Approach 1:
The patent applies partial holding of the reset pulse in each clock domain by synchronizing it to that domain's clock frequency and holding it for a predetermined number of cycles appropriate for that domain. Rather than holding it for the same extended period in all domains, it uses the minimum necessary duration for each, reducing overall reset time while ensuring completeness.
Data Source
AI summary
An integrated circuit and method for using a synchronous reset pulse to reset a circuitry comprising a plurality of clock domains are disclosed. For example, the method of the present disclosure provides a reset signal that is synched to one clock, takes the synchronous signal and resets circuits in a plurality of clock domains. In order to reset a portion of the circuit which is in a particular clock domain, the reset needs to be synchronized to the clock of the particular domain.