Synchronous State Machine With Aperiodic Clock For Boost Converters
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Solution Overview
Problem
Conventional boost converters employ asynchronous state machines, which are complex and sensitive to inputs, leading to potential metastable states, necessitating an improved state machine design.
Innovation Solution
A synchronous state machine is implemented using an analog timing controller with a glitch filter and a digital state machine that generates an aperiodic clock signal, comprising an input circuit, analog event circuit, clock generator, and enable circuit to process analog input signals and prevent metastable states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an asynchronous state machine is used in the controller, then the boost converter can operate with flexible timing, but the controller becomes complex and sensitive to inputs leading to metastable states
Solution Approach 1:
An aperiodic clock signal is introduced as an intermediary between the analog timing circuit and the digital state machine. This clock signal synchronizes the state machine's operation to the actual timing events in the boost converter, eliminating the need for complex asynchronous timing logic while preventing metastable states through proper clocked synchronization.
Solution Approach 2:
The patent replaces the mechanical/asynchronous timing mechanism with an electronic clocked system. The analog timing circuit generates timing events that are converted into a clock signal, which then drives the digital state machine in a synchronous manner, substituting the complex asynchronous mechanical timing with a simpler electronic clocking mechanism.
2Adaptability or versatility
If an asynchronous state machine is used, then timing flexibility is maintained, but the controller becomes sensitive to inputs causing metastable states
Solution Approach 1:
The aperiodic clock signal serves as a mediator that bridges the analog timing domain and the digital state machine domain. It allows the state machine to adapt to varying timing requirements while maintaining synchronous operation, thus preserving timing flexibility without the metastability issues of asynchronous design.
Solution Approach 2:
The system uses periodic clocked action (an aperiodic clock that still provides regular timing pulses) to synchronize state machine operations. This periodic clocking ensures that all state transitions occur at well-defined moments, reducing sensitivity to input signal timing variations and preventing metastable states.
3Reliability
If a synchronous state machine with aperiodic clock is implemented, then metastable states are reduced, but additional circuits (analog timing circuit, glitch filter, clock generator) are added
Solution Approach 1:
The patent merges multiple functions into integrated circuits: the analog timing circuit is combined with the digital state machine, the glitch filter is integrated into the timing control path, and the clock generator is merged with the state machine logic. This consolidation reduces the overall device complexity despite adding functional blocks.
Solution Approach 2:
The aperiodic clock signal serves multiple functions simultaneously: it synchronizes the state machine, provides timing reference for analog-to-digital conversion, and coordinates the operation of the glitch filter. This multi-functionality reduces the need for separate dedicated circuits for each function.
Data Source
AI summary
An apparatus is provided. The apparatus includes an analog timing controller and a digital state machine. An input circuit in the digital state machine is configured to receive a plurality of analog input signals, and an analog event circuit is coupled to the analog timing circuit, the glitch filter, and the input circuit. The analog event circuit and input circuit are configured to generate a composite event signal from the analog input signals and by using the analog timing circuit. The glitch filter is configured to receive the composite event signal. A clock generator also is coupled to the glitch filter, wherein the clock generator is configured to generate an aperiodic clock signal. The aperiodic clock signal is configured to be a synchronous clock signal for the digital state machine.