Synchrophasor Data Management System Latency Reduction

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Solution Overview

Problem

Current systems for wide area monitoring of electrical grid infrastructure face challenges in efficiently managing and communicating synchrophasor data, particularly in terms of latency and protocol compatibility across different devices and geographic locations.

Innovation Solution

The implementation of a Synchrophasor Data Management System (SDMS) that includes a Synchrophasor Processor System (SPS) with virtual PMU functionality, capable of receiving and transforming data from Phasor Measurement Units (PMUs), aggregating it into time-aligned datasets, and transmitting these datasets across various protocols, including IEEE C37.118X and IEC 61850-90-5, to external devices such as PDCs and super PDCs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If data is transmitted between PDCs, PMUs, and super PDCs using IEEE C37.118X protocols, then wide area monitoring coverage is achieved, but data latency increases

Engineering Contradiction:

Improvewide area monitoring coverageVSAvoiddata latency

Core Design Contradiction:

Area of stationary objectVSLoss of time

Solution Approach 1:

The system segments the synchrophasor data management into multiple hierarchical levels (PMUs at distribution level, PDCs at substation level, and super PDC at control center level). Each level processes and filters data locally before transmission, reducing the total data volume and communication latency while maintaining wide area coverage.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The PDC performs preliminary data processing, filtering, and validation before transmitting data to the super PDC. This preliminary action reduces the data volume and ensures data quality, thereby reducing transmission latency and improving overall system efficiency.

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If multiple protocols (IEEE C37.118X and IEC 61850-90-5) are supported for data transmission, then protocol compatibility is improved, but device complexity increases

Engineering Contradiction:

Improveprotocol compatibilityVSAvoiddevice complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The PDC is designed with multi-functionality to support multiple protocols (IEEE C37.118X and IEC 61850-90-5) simultaneously. This universal design allows the same device to operate in different protocol environments without requiring separate dedicated devices, improving compatibility while managing complexity through standardized processing architectures.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9684700B2Systems for synchrophasor data managment

Publication Date: 2017.06.20 GE INFRASTRUCTURE TECH LLC

AI summary

A system includes a Synchrophasor Data Management System (SDMS), in which the SDMS includes a Synchrophasor Processor System (SPS). The SPS includes a Phasor Data Concentrator (PDC) configured to receive a first plurality of inputs from a first Phasor Measurement Unit (PMU), transform at least one of the first plurality of inputs into a first time aligned output by time aligning the at least one of the first plurality of inputs. The SPS further includes a virtual PMU configured to aggregate the first time aligned output into a PMU dataset, in which the SPS is configured to transmit the PMU dataset to a second PMU, an external PDC, a super PDC, or a combination thereof.