Staged-Parallel Syndrome Circuit for High-Rate Frame Detection
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Solution Overview
Problem
Existing methods for detecting frame boundaries in data transmission, such as the brute-force technique and Iwamura's quick search, face challenges at high data rates due to increased circuit complexity and processing time, especially when using multiple-bit word inputs.
Innovation Solution
A staged-parallel structure of syndrome computation circuits that computes a fraction of syndromes in one clock cycle using two frame buffers, reducing circuit complexity while maintaining a shorter searching time compared to brute-force methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If brute-force technique is used for frame boundary detection, then detection completeness is improved, but circuit complexity and processing time increase significantly at high data rates
Solution Approach 1:
The patent segments the frame boundary detection process into multiple stages with different search strategies. The first stage uses a simplified syndrome computation for rapid initial search, while subsequent stages perform more thorough verification. This segmentation allows the system to achieve comprehensive detection without requiring full brute-force complexity throughout the entire detection process.
Solution Approach 2:
The patent applies partial action by performing syndrome computation on only a subset of candidate frame boundaries in the initial search stage. Instead of computing syndromes for all possible positions (excessive action), the system strategically selects candidate positions based on predefined patterns or probability, reducing circuit complexity while maintaining adequate detection reliability.
2Productivity
If multiple-bit word inputs are used to increase processing speed, then productivity is improved, but circuit complexity increases due to additional correction circuits
Solution Approach 1:
The patent segments the multiple-bit syndrome computation into smaller sub-computations that can be performed using existing single-bit syndrome computation circuits. By dividing the wide-bit processing into multiple smaller operations executed in sequence or parallel using resource sharing, the system achieves high processing speed without proportionally increasing circuit complexity.
Solution Approach 2:
The patent designs the syndrome computation circuit to be universal and reconfigurable, capable of handling multiple-bit inputs through a small number of core computational units. The same circuit structures serve multiple functions by processing different bit positions and frame boundary candidates, eliminating the need for separate correction circuits for each bit position and thereby reducing overall circuit complexity.
3Loss of time
If Iwamura's quick search method is used, then searching time is reduced, but circuit complexity increases and resource efficiency decreases
Solution Approach 1:
The patent uses copying by maintaining simplified replicas or shadow versions of frame data in buffer memory that can be rapidly accessed for syndrome computation. Instead of processing the full high-speed data stream directly, the system works with copied representations of candidate frames, enabling quick search operations with reduced circuit complexity since the copying operation itself is simple memory access rather than complex processing.
Data Source
AI summary
One embodiment relates to a frame detection circuit for detecting a frame boundary. The circuit includes at least two frame buffers and a staged-parallel structure of syndrome computation circuits that computes a number of syndromes in one cycle. The two frame buffers are each one word in width. The number of syndromes computed in one cycle by the cascaded series is a fraction of a number of bits in one word. Another embodiment relates to a method for detecting a frame boundary. Another embodiment relates to a method for computing a current syndrome. Other embodiments, aspects, and features are also disclosed.