Syndrome Generator Circuit for Compressed Memory Test Data
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Solution Overview
Problem
In semiconductor memory device manufacturing, the operation test to determine normal address accessibility involves compressing test read data to reduce testing time, but this increases chip size due to the need for dedicated buses or processing circuits to transfer fail data.
Innovation Solution
The semiconductor memory device incorporates a compression logic circuit that compresses test read data and generates fail data, which is then encoded by ECC circuits, eliminating the need for a dedicated bus or processing circuit for fail data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If test read data is compressed to reduce testing time, then productivity is improved, but device complexity increases due to the need for dedicated bus or processing circuit
Solution Approach 1:
The existing data I/O lines are made multi-functional by enabling them to transfer both normal data and compressed fail data. The data I/O lines that normally carry read/write data are repurposed to carry compressed fail data during test operations, eliminating the need for dedicated fail data transfer paths while maintaining the ability to perform both normal operations and accelerated testing.
2Reliability
If dedicated bus is provided for fail data transfer, then reliability is improved, but area of stationary object increases
Solution Approach 1:
The fail data transfer function is merged with the existing data I/O infrastructure. The same data I/O lines used for normal read/write operations are combined with the fail data transfer function, allowing reliable data transfer without requiring separate dedicated physical paths. The compression logic consolidates multiple fail data bits into fewer transmitted bits, maintaining reliability while reducing the area required for data transfer infrastructure.
Data Source
AI summary
An apparatus that includes a memory cell array, an I/O terminal supplied with an original write data in a normal operation, a compression logic circuit configured to generate a compressed test data in a test operation based on a test read data read from the memory cell array, and a syndrome generator configured to generate a first syndrome based on the original write data in the normal operation and generate a second syndrome based on the compressed test data in the test operation.