Syndrome Generator Pre-Charging for Faster Memory Error Detection
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Solution Overview
Problem
Existing error detection schemes in memory devices, such as those using XOR gates, face delays that hinder their speed due to the need for numerous comparisons, which can be unpredictable and slow down the error detection process.
Innovation Solution
A memory device and method that utilize a syndrome generating circuit with pre-charged input terminals, set to a predetermined logic state by latch circuits, to optimize the switching speed of XOR gates by limiting logic state changes to high-to-low transitions, thereby reducing delay overhead and improving error detection performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection schemes use XOR gates to perform comparisons between original data and spare data, then error detection capability is achieved, but the delay of XOR gates becomes the main limiting factor for detection speed
Solution Approach 1:
The patent applies pre-charging to set input terminals to a predetermined logic state (e.g., logic 0) before the actual error detection operation begins. This preliminary action ensures that when data bits are applied, the XOR gates undergo predictable transitions, optimizing switching speed and reducing propagation delay throughout the detection process
2Reliability
If a large number of comparisons are performed to detect errors in data bits, then comprehensive error detection is achieved, but the speed of error detection scheme depends mainly on delay of XOR gates
Solution Approach 1:
By pre-charging all input terminals to a known logic state before data input, the patent eliminates unpredictable propagation delays that would occur if inputs started from unknown states. This preliminary setup enables faster and more consistent operation across all XOR gates in the comparison network
Solution Approach 2:
The patent employs periodic pre-charging cycles synchronized with data input operations. Each detection cycle begins with a pre-charge phase that resets input terminals, followed by the actual comparison phase, creating a rhythmic operational pattern that optimizes timing and reduces overall delay
Data Source
AI summary
A memory device includes a syndrome generating circuit and a plurality of latch circuits. The syndrome generating circuit includes a plurality of input terminals and plurality of logic circuits. The latch circuits are coupled to the syndrome generating circuit and are configured to set the input terminals of the syndrome generating circuit to a predetermined logic state according to a pre-charge reset signal. The latch circuits are configured to provide a plurality of data bits to the input terminals of the syndrome generating circuit after the input terminals of the syndrome generating circuit are set to the predetermined logic state. The syndrome generating circuit is configured to generate a syndrome bit based on the data bits by the logic circuits, wherein the syndrome bit indicates a presence of an error bit among the data bits.