Synergistic IC Design Method Using Standard and Non-Standard Cell Libraries
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Solution Overview
Problem
Current semiconductor integrated circuit (IC) design and manufacturing processes face challenges in efficiently optimizing the combination of standard and non-standard cells to meet complex functional specifications, particularly in translating high-level behavior specifications into physical layouts that satisfy performance, power, and area constraints, especially with the increasing complexity of modern circuits.
Innovation Solution
The synergistic design method involves forming standard and non-standard cell libraries, where standard cells perform Boolean logic operations and non-standard cells perform complex functions, using a conversion process for standard cells to generate a Boolean network and applying direct mapping for non-standard cells to create a gate-level netlist, thereby optimizing the IC design flow through technology mapping, placing, routing, and timing analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If highly automated processes are used to select cells from a library to meet functional specifications, then design productivity is improved, but the ability to optimize power, performance, and area constraints deteriorates
Solution Approach 1:
The patent segments the cell library into two distinct categories: standard cells with known Boolean logic operations and non-standard cells with complex functions. This segmentation allows the automated design process to handle different cell types appropriately, maintaining productivity while enabling optimization of power, performance, and area constraints through targeted mapping strategies for each cell category.
Solution Approach 2:
The patent introduces an intermediary conversion process that translates high-level behavior specifications into a gate-level netlist. This intermediary step serves as a bridge between the automated cell selection process and the final physical layout, enabling optimization of power, performance, and area constraints without compromising design productivity.
2Productivity
If the size of semiconductor device components is reduced to increase functional density, then production efficiency is improved and costs are lowered, but the difficulty of detecting and measuring features increases
Solution Approach 1:
The patent performs preliminary technology mapping and placement operations during the design phase, before fabrication. By converting the gate-level netlist into an optimized physical layout with precise component locations and interconnections, the design data is prepared in advance with sufficient detail to guide manufacturing processes, enabling production efficiency gains from scaling without compromising the ability to detect and measure finer features during fabrication.
3Adaptability or versatility
If standard cells are converted through a conversion process to generate Boolean networks, then design flexibility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent extracts the conversion process specifically for standard cells, separating it from the handling of non-standard cells. By taking out and applying the conversion process only where needed (for standard cells to generate Boolean networks), the patent achieves design flexibility for standard cell optimization while avoiding unnecessary manufacturing complexity that would result from applying the same process to all cell types.
Data Source
AI summary
A synergistic design method for an integrated circuit (IC) is provided. The synergistic design method includes forming a standard cell library and a non-standard cell library, implementing an IC design process from a high-level behavior specification through a gate-level netlist to a physical layout, and verifying the physical layout to fabricate the IC. Each standard cell of the standard cell library performs a Boolean logic operation. Each non-standard cell of the non-standard cell library performs a complex function beyond the Boolean logic operation. A conversion process is executed for translating a circuit function into a Boolean network to generate the gate-level netlist based on the standard cells of the standard cell library corresponding to the circuit function. A direct mapping is executed on the non-standard cell by skipping the conversion process during the IC design process to generate the gate-level netlist.