Synthesis Flow Formal Verification Segmentation
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Solution Overview
Problem
Formal verification in the synthesis flow of integrated circuits is complex and time-consuming, often failing to establish equivalency between input and output due to significant differences in their representations.
Innovation Solution
The synthesis flow is subdivided into multiple transformations, with each transformation's input and output converted into hardware description language (HDL) representations for per-transformation formal verification, allowing for incremental and more efficient comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification is performed on the entire synthesis flow input and output, then verification completeness is improved, but verification time and complexity increase significantly
Solution Approach 1:
The synthesis flow is divided into multiple discrete transformations, and formal verification is applied to each transformation individually rather than to the entire flow. This segmentation reduces the verification problem size at each step, making verification more manageable and faster while maintaining overall verification completeness through cumulative verification of all transformations.
2Measurement precision
If formal verification compares entire synthesis input and output, then verification thoroughness is improved, but computational complexity increases
Solution Approach 1:
The verification process is segmented into multiple smaller verification tasks, one for each transformation in the synthesis flow. Each task compares the input and output of a single transformation, significantly reducing the computational complexity compared to verifying the entire synthesis flow as a single large-scale comparison.
3Productivity
If per-transformation verification is implemented, then verification speed is improved, but process complexity increases
Solution Approach 1:
The synthesis flow is segmented into discrete transformations that can be verified independently and in sequence. This segmentation enables faster verification by focusing on smaller, localized changes at each transformation step rather than analyzing the entire synthesis process as one large comparison.
Solution Approach 2:
HDL representations of transformation inputs and outputs are generated in advance of the verification step. This preliminary preparation of standardized HDL formats for each transformation facilitates faster comparison operations during the actual verification process.
Data Source
AI summary
Processing a circuit design includes generating a transformation output from a transformation input for each of a plurality of transformations of a synthesis flow applied to the circuit design. For each transformation, the transformation input and the transformation output represent the circuit design. At least one circuit element is changed from the transformation input to the transformation output. For each transformation, a hardware description language representation of the transformation input and a hardware description language representation of the transformation output are generated. For each transformation, determining whether the hardware description language representation of the transformation input is equivalent to the hardware description language representation of the transformation output.