Synthesized Clock Synchronization Without Recovered Clock Buffering
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Solution Overview
Problem
Current clock synchronization methods in network devices face challenges with inaccurate latency measurements due to unsynchronized clocks, particularly in devices with multiple ports or lanes, where buffering recovered clocks introduces noise and unnecessary jitter, complicating the synchronization process.
Innovation Solution
A network device with frequency generation circuitry that includes a phase-locked loop (PLL) and receivers to recover remote clocks, a controller to identify the master clock and adjust the local clock iteratively to match it, and a closed feedback loop with a frequency mixer to reduce clock differential, thereby simplifying synchronization and minimizing noise and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If recovered clocks are buffered in devices with multiple ports or lanes, then clock synchronization can be achieved, but noise and jitter are introduced
Solution Approach 1:
The patent extracts the harmful buffering operation from the clock synchronization process. Instead of buffering recovered clocks which introduces noise and jitter, the system directly uses the recovered clocks from individual ports/lanes to generate local clocks independently, eliminating the source of degradation while maintaining synchronization capability.
Solution Approach 2:
The patent segments the clock synchronization process by allowing each port or lane to independently recover and process its own clock signal through separate phase-locked loops. This segmentation prevents the accumulation of noise and jitter that would occur in a centralized buffering approach, as each segment operates independently without interfering with others.
2Reliability
If multiple recovered clocks are multiplexed to achieve synchronization, then clock alignment can be achieved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a standardized phase-locked loop architecture that can process any recovered clock signal from any port or lane in the same manner. Each PLL is multi-functional, capable of locking to different input frequencies and generating appropriate local clocks, eliminating the need for complex multiplexing and selection logic.
Solution Approach 2:
Each port or lane independently performs clock recovery and generation through its own phase-locked loop without requiring centralized control or multiplexing. The system achieves synchronization through self-service operation of distributed PLLs, significantly reducing the complexity of clock management infrastructure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate clock synchronization across network devices without multiplexing recovered clocks, reducing noise and jitter, and scaling effectively for devices with multiple dies or ports, ensuring precise clock alignment with the master clock.
Implementation Method 1
a phase-locked loop (PLL) configured to generate a local clock based on the clock signal
Implementation Method 2
a frequency mixer configured to combine the control signal from the controller with an output of the switching circuitry to generate the clock signal as a combined signal
Data Source
AI summary
In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.