Frequency Synthesizer Channel Code Correction for Reliable PLL Lock
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Solution Overview
Problem
Frequency synthesizers often fail to properly lock onto a target frequency due to erroneous channel code determinations during the coarse tuning process, leading to impaired system performance and the need for external error correction measures.
Innovation Solution
A frequency synthesizer design that includes a frequency decider capable of correcting channel code errors during coarse tuning, using a binary search tree to determine the correct channel code and a phase locker for fine tuning, thereby ensuring accurate selection of the target frequency without external intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a frequency synthesizer uses a two-step tuning process (coarse tuning with channel code selection followed by fine tuning with phase locking), then it can efficiently select from a wide band of frequencies, but it becomes vulnerable to channel code errors that cause lock failures and require external error correction
Solution Approach 1:
The patent implements feedback by continuously monitoring the frequency synthesis process and using the output frequency information to verify and correct channel code selections. The system feeds back the actual frequency measurements to the channel code decision logic, allowing it to detect and correct erroneous channel code determinations without external intervention, thus resolving the contradiction between efficient two-step tuning and reliable lock acquisition
Solution Approach 2:
The frequency synthesizer performs self-diagnosis and self-correction by internally detecting channel code errors through frequency measurement and automatically correcting the channel code selection. This self-service capability eliminates the need for external error correction measures while maintaining the efficient two-step tuning process, thereby improving reliability without sacrificing productivity
2Reliability
If external error correction measures or lengthy channel code search routines are implemented to correct erroneous channel codes, then lock failures can be recovered from, but the responsiveness of the frequency synthesizer is greatly diminished
Solution Approach 1:
The patent applies preliminary action by pre-establishing the feedback mechanism and error detection logic within the frequency synthesizer before operation. The system is pre-configured to automatically detect and correct channel code errors using internal frequency measurements, so when errors occur, correction can begin immediately without waiting for external intervention or initiating lengthy search routines, thus maintaining high responsiveness while ensuring error recovery
Solution Approach 2:
The system skips the lengthy external error correction process by implementing rapid internal error detection and correction. Through continuous frequency monitoring and immediate feedback to the channel code selection logic, the system can quickly identify and correct errors in real-time, rushing through what would otherwise be a slow external correction process and thereby preserving responsiveness
Data Source
AI summary
A voltage controlled oscillator (VCO) in a frequency synthesizer generates an output signal having a target frequency by being coarse tuned in accordance with a channel code derived through a binary tree search. Thereafter, the output signal of the VCO may be further tuned using a phase lock loop (PLL) circuit. Each stage of the binary tree search includes a comparison step that determines a channel code bit, and another step that confirms that the channel code converges to a final channel code within an established stage range value.