Frequency Synthesizer Dual-Clock Segmentation
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Solution Overview
Problem
Frequency synthesizers face limitations in generating a wide frequency range due to the fixed hardware of analog PLLs and dividers, leading to high power consumption, misalignment issues, and lengthy factory test times, especially when dealing with low common frequencies and long divider chains.
Innovation Solution
A frequency synthesizer architecture using two clocks with a fixed frequency ratio, where a low-frequency clock is used for counting and decoding, and a higher-frequency clock outputs the results, allowing for flexible division ratios, reduced power consumption, and quicker alignment, implemented with a counter, adder, decoder, and parallel-serial converter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If counters and dividers are used to extend frequency range, then output frequency range is increased, but power consumption increases due to high clock rates
Solution Approach 1:
The patent divides the frequency synthesis function into two separate modules: a VCO module that generates high-frequency clock signals, and a counter module that performs division operations. By separating these functions, the counter operates at lower frequencies while the VCO handles high-frequency generation, thus reducing overall power consumption while maintaining extended frequency range capability.
Solution Approach 2:
The patent introduces a buffer circuit as an intermediary between the VCO output and the counter input. This buffer isolates the high-frequency VCO signal from the counter, allowing the counter to operate at reduced frequencies while still achieving the desired output frequency range through the combination of VCO multiplication and counter division.
2Ease of manufacture
If fixed hardware dividers are implemented in silicon, then manufacturing is simplified, but adaptability to different frequency requirements is lost
Solution Approach 1:
The patent implements programmable counters with configurable division ratios, replacing fixed hardware dividers. These dynamic counters can be programmed through control registers to achieve different division ratios, allowing the same hardware to adapt to various frequency requirements while maintaining the benefits of integrated silicon implementation.
Solution Approach 2:
The patent uses control registers and decoding logic to dynamically change the division ratio parameter of the counters. By modifying the programmed values in these registers, the system can adapt to different frequency requirements without hardware changes, combining ease of manufacture with frequency range flexibility.
3Adaptability or versatility
If long divider chains are used to achieve high division ratios, then frequency range is extended, but factory test time increases
Solution Approach 1:
The patent achieves high division ratios by cascading multiple counter modules rather than using a single long divider chain. Each counter module can be independently tested and calibrated, significantly reducing factory test time compared to testing a single lengthy divider chain, while still achieving the required overall division ratio through the series connection.
4Adaptability or versatility
If multiple analog PLLs are started simultaneously, then frequency synthesis is achieved, but output misalignment occurs due to different locking trajectories
Solution Approach 1:
The patent implements a startup control mechanism that sequentially enables multiple PLLs rather than starting them simultaneously. By controlling the enable timing of each PLL through control registers, the system ensures that all PLLs lock to their respective frequencies in a controlled sequence, preventing output misalignment while maintaining the capability for multi-PLL frequency synthesis.
Data Source
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AI summary
A frequency synthesizer includes a first clock running at a frequency fCLK1, a second clock running at a frequency fCLK2, wherein frequency fCLK2 is higher than frequency fCLK1, the frequencies having a fixed ratio QFB = fCLK2/ fCLK1; and a counter driven by the first clock. A decoder for produces QFB output values in parallel for each cycle of the first clock, and parallel-serial converter serially outputs these QFB output values at the frequency of the second clock.