Frequency Synthesizer Edge Alignment for Faster PLL Locking
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Solution Overview
Problem
Existing frequency synthesizers have variable and often long locking times due to random initialization, which affects start-up times and power consumption, as they rely on optimizing parameters like reference-clock frequency, charge pump current, and VCO gain without a controlled starting point.
Innovation Solution
Disabling and then enabling the frequency synthesizer elements upon detection of a transition edge in the reference-clock signal, using an edge-detection circuit to synchronize the start of the phase-locked loop, thereby controlling the initialization point and reducing locking time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the loop is closed at a random moment, then the frequency synthesizer can start operation immediately, but the locking time becomes variable and can be relatively long
Solution Approach 1:
The patent applies preliminary action by detecting the transition edge of the reference-clock signal before enabling the phase-locked loop. This edge-detection mechanism prepares the system by identifying the optimal starting point in advance, ensuring that the loop is enabled at a consistent phase point rather than at a random moment. This preliminary detection eliminates the variability in locking time while maintaining rapid start-up operation.
2Loss of time
If the locking time is reduced through parameter optimization, then the start-up time decreases, but the start-up power consumption increases
Solution Approach 1:
The patent changes the temporal parameter of loop enabling from random timing to edge-synchronized timing. By aligning the loop enablement with the transition edge of the reference-clock signal, the system achieves consistent and reduced locking time without requiring increases in charge pump current or VCO gain, thereby avoiding the associated power consumption penalties.
3Speed
If the frequency synthesizer elements are enabled immediately, then the system responds quickly, but the synchronization with the reference-clock signal is inconsistent
Solution Approach 1:
The patent implements feedback by using the transition edge of the reference-clock signal as a trigger for enabling the phase-locked loop. The edge-detection circuit continuously monitors the reference-clock signal and provides feedback information about its state, enabling the loop only when the signal is at the appropriate phase point. This feedback mechanism ensures both rapid response and consistent synchronization.
Solution Approach 2:
The system performs preliminary detection of the reference-clock signal's transition edge before enabling the loop elements. This preliminary action ensures that when the loop is enabled, it does so at a consistent and optimal phase point, guaranteeing reliable synchronization while maintaining fast response time.
Data Source
AI summary
A frequency synthesizer (50, 70) including an edge-detection circuit (51, 60) for disabling elements of the frequency synthesizer (50, 70) prior to start-up. The edge-detection circuit detects a transition edge of a reference-clock signal (ref_clk) of the frequency synthesizer (50, 70) and enables elements of the frequency synthesizer (50, 70) upon the detection of the transition edge.