Digital Frequency Synthesizer Phase-to-Amplitude Conversion
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Solution Overview
Problem
Direct Digital Frequency Synthesizers (DDFS) face challenges in achieving a high Spurious Free Dynamic Range (SFDR) with low hardware complexity, often requiring high circuit complexity and computational power.
Innovation Solution
A method for phase-to-amplitude conversion using a combination of linear interpolation and a second-order sinusoidal term to correct errors, reducing the need for large ROM look-up tables and arithmetic circuitry, thereby achieving efficient storage and computational performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a wide phase accumulator is used to satisfy frequency resolution requirements, then frequency resolution is improved, but LUT size increases significantly
Solution Approach 1:
The phase-to-amplitude conversion is segmented into multiple stages: first a coarse conversion using a smaller LUT, then refinement using interpolation and error correction terms. This divides the single large LUT operation into multiple smaller operations that achieve the same result with reduced storage requirements.
Solution Approach 2:
The invention changes the representation parameters by using difference tables and error correction terms instead of storing complete amplitude values. The LUT stores only differential values and correction coefficients, which require fewer bits while maintaining the same conversion accuracy.
2Quantity of substance
If polynomial approximation techniques are used to reduce LUT size, then storage requirements are reduced, but computational complexity increases
Solution Approach 1:
The invention replaces complex polynomial arithmetic with simpler operations: lookup table access, addition, and bit-shifting. The error correction mechanism uses basic arithmetic operations instead of complex multiplication and division, significantly reducing the computational burden while maintaining accuracy.
Solution Approach 2:
The invention introduces intermediate difference tables and error correction terms as mediators between the phase accumulator and final amplitude output. These intermediaries break down the complex conversion into manageable steps that can be executed with simple arithmetic operations.
3Measurement precision
If large LUT and arithmetic circuitry are used to achieve high SFDR, then SFDR performance is improved, but hardware complexity increases
Solution Approach 1:
The high-precision conversion is segmented into multiple passes: a coarse conversion followed by error correction passes. Each pass uses simpler circuitry, but the combination achieves the same SFDR performance as a single complex conversion stage would require.
Solution Approach 2:
The invention uses feedback through error correction terms that compensate for inaccuracies in the coarse conversion. The difference tables and correction mechanisms provide feedback loops that iteratively improve the amplitude accuracy without requiring a single large complex LUT.
Data Source
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AI summary
A method for use in a digital frequency synthesizer (100), the method comprising phase to amplitude conversion (120) of an output value of a phase accumulator (110) in said synthesizer (100), said conversion being carried out as an approximation (y) of a phase value (x) which corresponds to said output amplitude value, the method being characterized in that the approximation comprises a combination of a linear interpolation value and a second order sinusoidal value, the second order sinusoidal value being used as an error term to correct for errors in the linear interpolation value.