Synthesizing Assert Statements into Netlist Elements
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Solution Overview
Problem
Conventional approaches to implementing register transfer level (RTL) circuit designs on prototyping and emulation platforms do not support assert statements, leading to undetected error conditions and increased debugging time, as synthesis processes ignore these statements as non-synthesizable constructs.
Innovation Solution
A method that synthesizes assert statements into netlist elements, including sticky registers and detection circuitry, to capture logic states of conditional expressions, and integrates assertion-enable and readback circuitry to store and output assertion hits, enabling debugging support on prototyping and emulation platforms without modifying the RTL specification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If assert statements are included in RTL specification for debugging, then debugging capability is improved, but synthesis compatibility deteriorates because conventional synthesis processes ignore these statements as non-synthesizable constructs
Solution Approach 1:
The patent introduces an intermediary synthesis process that acts as a mediator between the RTL specification containing assert statements and the final netlist. This intermediate synthesis stage translates assert statements into synthesizable netlist elements (detection circuitry and sticky registers) before final implementation, enabling both debugging capability and synthesis compatibility to coexist.
Solution Approach 2:
The patent changes the parameter state of assert statements from 'non-synthesizable' to 'synthesizable' by transforming them into equivalent hardware circuitry. The assert statements are converted into detection circuitry with associated sticky registers, fundamentally altering their implementability parameter while preserving their original debugging function.
2Adaptability or versatility
If assert statements are synthesized into netlist elements, then portability to prototyping platforms is improved, but device complexity increases due to addition of detection circuitry and sticky registers
Solution Approach 1:
The patent segments the assert statement functionality into distinct modular components: detection circuitry that evaluates conditional expressions and sticky registers that capture and hold assertion hit states. This segmentation allows the debugging functionality to be distributed across multiple standardized hardware blocks, improving portability while managing complexity through modular design.
Solution Approach 2:
The patent creates a simplified copy of the assertion evaluation logic in hardware form (detection circuitry) that mirrors the software-based assert statement behavior. This hardware copy enables prototyping platform portability by replicating the debugging functionality in a form compatible with FPGA and emulator devices, accepting increased device complexity as a trade-off for achieving cross-platform portability.
3Measurement precision
If detection circuitry and sticky registers are added for each assert statement, then assertion hit capture accuracy is improved, but resource utilization increases
Solution Approach 1:
The patent designs detection circuitry and sticky registers as universal, reusable hardware templates that can be instantiated for each assert_statement. Each assert statement receives dedicated detection circuitry that evaluates its specific conditional expression and a sticky register that captures its assertion hit state, ensuring precise tracking of each assertion while using standardized modular building blocks that optimize resource utilization through design reuse.
Data Source
AI summary
A method, system, and circuit arrangement involve synthesizing a circuit design specified in a register transfer level (RTL) specification into a netlist. The RTL specification includes an assert statement that specifies a conditional expression involving one or more signals specified in the circuit design to be checked during simulation, and the synthesizing includes synthesizing the assert statement into netlist elements. The design tool places and routes the netlist into a circuit design layout and generates implementation data from the layout.