Synthetic Clock Timing Test for SDRAM Setup and Hold Measurement
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Solution Overview
Problem
In synchronous dynamic random access memory (SDRAM) devices, accurately measuring setup and hold times for data with respect to internal clock signals is challenging due to the need for precise timing and synchronization with external clock signals, which can be complex and time-consuming.
Innovation Solution
A semiconductor system comprising a synthetic clock generator and a flag signal generator that creates a synthetic clock signal with different pulse widths to latch a test signal, allowing simultaneous measurement of setup and hold times by enabling a test enablement signal, clock signal, and test signal, facilitating the generation of a flag signal for precise timing analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional measurement methods are used for setup and hold times, then measurement accuracy may be maintained, but test time is excessively long and efficiency is low
Solution Approach 1:
The patent uses periodic clock signals (first clock signal and second clock signal with different phases) to systematically probe setup and hold times across multiple cycles. By applying periodic test patterns synchronized with the clock, the measurement process becomes efficient and repeatable, reducing total test time while maintaining accuracy through multiple measurement opportunities
Solution Approach 2:
The patent divides the measurement process into separate dedicated circuits: a setup time measurement circuit and a hold time measurement circuit. Each circuit is independently configured to measure specific timing parameters, allowing parallel or sequential execution without interfering with each other, thus improving overall test efficiency
2Measurement precision
If separate measurement circuits are not used, then device complexity is reduced, but measurement accuracy and reliability deteriorate
Solution Approach 1:
The patent divides the measurement process into separate dedicated circuits: a setup time measurement circuit and a hold time measurement circuit. Each circuit is independently configured to measure specific timing parameters, allowing parallel or sequential execution without interfering with each other, thus improving overall test efficiency
Solution Approach 2:
The measurement circuits are designed to be controlled by a test enablement signal, allowing them to be activated only when needed. The same circuit structure can measure different timing parameters (setup time, hold time) by changing the clock signal phase relationships, providing multi-functionality without requiring completely separate dedicated hardware for each measurement type
3Reliability
If the test signal is not synchronized with the clock signal, then circuit design is simpler, but measurement reliability and accuracy are compromised
Solution Approach 1:
The patent employs synchronization circuits that align the test signal phase with the clock signal phase. By continuously monitoring and adjusting the test signal timing based on clock edges, the system ensures reliable correlation between data transitions and clock events, making measurements of setup and hold times accurate and repeatable
Solution Approach 2:
The synchronization circuits perform preliminary alignment of the test signal with the clock signal before the actual measurement process begins. This preliminary phase synchronization ensures that when measurements are taken, the relationship between test signal transitions and clock edges is already established, improving measurement reliability without requiring complex real-time adjustments during measurement
Data Source
AI summary
Semiconductor devices are provided. One of the semiconductor devices may include a synthetic clock generator and a flag signal generator. The synthetic clock generator may be configured to generate a synthetic clock signal in response to a test enablement signal. The synthetic clock signal may be generated from a clock signal to include a first section pulse and a second section pulse having different pulse widths. The flag signal generator may be configured to latch a test signal in response to the synthetic clock signal to generate a flag signal.