System Compiler for Network Switch Accelerator Integration
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Solution Overview
Problem
In large data centers, network switches face challenges in efficiently performing complex functions such as compression, decompression, IP security, encryption, decryption, load-balancing, and routing due to high overhead in launching OpenCL kernels, which can become bottlenecks in high-frequency operations.
Innovation Solution
A system compiler is used to compile logic for both domain-specific languages (DSLs) like P4 for core switching logic and Turing-complete languages like OpenCL for accelerators, with dedicated I/O channels for direct data interchange, allowing implicit kernel launch and continuous operation of accelerators, reducing overhead and optimizing data operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If OpenCL kernels are launched for accelerator functions, then complex network functions can be performed, but high overhead becomes a bottleneck in high-frequency operations
Solution Approach 1:
The patent pre-loads accelerator functions into on-chip memory before they are needed, so that when a kernel launch is required, the function is already available in fast memory rather than being fetched from external memory. This preliminary preparation eliminates the memory access delay that contributes to launch overhead.
Solution Approach 2:
The patent merges the kernel launch mechanism with the data path by integrating control logic directly into the switching fabric. This allows kernel launches to be initiated through existing data path infrastructure rather than requiring separate control channels, reducing the overhead of launch operations.
2Productivity
If DMA buffers and memory operations are used for data interchange, then data transfer between switch and accelerator is enabled, but overhead increases and efficiency decreases
Solution Approach 1:
The patent extracts the data interchange function from the traditional DMA buffer path and implements it directly through the switching fabric. By removing the intermediate memory buffering step and allowing direct packet routing between ingress/egress ports and accelerator functions, the system eliminates unnecessary memory operations and reduces overhead.
Solution Approach 2:
The switching fabric acts as an intermediary that directly connects data sources and destinations without requiring intermediate memory buffers. This mediator capability allows packets to be routed and processed in-flight, eliminating the need for DMA buffers and associated memory operations.
3Ease of operation
If accelerators operate with explicit kernel launches, then function execution is controlled, but continuous operation and efficiency are reduced
Solution Approach 1:
The patent enables accelerators to operate continuously by pre-loading functions and maintaining them in ready state within on-chip memory. Once a function is loaded, the accelerator can execute multiple packets back-to-back without interruption or re-loading, achieving continuous useful action and maximizing throughput.
Data Source
AI summary
In an example, there is disclosed a computing system, including: a processor; a memory; a configuration interface to a logic configuration unit; and a system compiler including: a first block compiler to compile logic for a first logical block in a first language, the first language being a domain-specific language (DSL) and the first logical block being switching logic for a network switch; a second block compiler to compile logic for a second logical block in a second language, the second language being a non-DSL and providing an external accelerator method not supported by the first language; and an interface compiler to define input/output channels for encapsulated data interchange between the first logical block and the second logical block, wherein the encapsulated data interchange is to target a resident instance of the external accelerator method.