System Decoder for Direct AI Accelerator Synchronization
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Solution Overview
Problem
Existing systems for deep learning training in AI systems face substantial overhead and resource waste due to cumbersome communication between accelerators, which is exacerbated in edge cloud computing environments with limited resources, leading to performance bottlenecks and thermal issues.
Innovation Solution
The system decoder extends the accelerator inter-chip link (ICL) with programmable logic to enable transparent communication between AI appliances across different platforms, abstracting physical and network channels, and facilitating seamless operation within scaled-up or scaled-down deployments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional CPU-mediated communication is used between accelerators, then system compatibility is maintained, but communication overhead increases and performance decreases
Solution Approach 1:
The patent introduces a system decoder as an intermediary component that mediates communication between accelerators. This decoder translates between different accelerator protocols and the host system protocol, enabling direct accelerator-to-accelerator communication without CPU intervention and eliminating the performance bottleneck of traditional CPU-mediated communication
Solution Approach 2:
The patent replaces the mechanical CPU-mediated communication system with a direct accelerator-to-accelerator communication system using the system decoder. This substitution eliminates the overhead of CPU involvement and enables high-speed direct communication between accelerators for training tasks
2Productivity
If accelerators communicate through host memory, then system simplicity is maintained, but resource waste increases and throughput decreases
Solution Approach 1:
The patent extracts the communication function from the host memory path and implements it directly at the accelerator level through the system decoder. This extraction eliminates the need for data to traverse host memory, reducing resource waste and enabling high-throughput direct accelerator communication
Solution Approach 2:
The patent segments the communication path by introducing the system decoder as a separate component between accelerators and the host system. This segmentation allows accelerators to communicate directly without involving host memory resources, improving throughput and reducing resource waste
3Adaptability or versatility
If fixed hardware configuration is used, then system stability is maintained, but adaptability to dynamic workloads decreases
Solution Approach 1:
The patent implements dynamics by enabling the system to adapt its configuration based on workload requirements. The system decoder allows dynamic composition of accelerators into different topologies and configurations, transforming a static hardware system into a dynamic, workload-adaptive system
Solution Approach 2:
The system decoder provides universality by serving as a universal interface that can handle multiple accelerator types and communication protocols. This universal component enables a single system to adapt to various workload configurations without requiring hardware changes, improving versatility while managing complexity
Data Source
AI summary
There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.