Dynamic System Directory Capacity for Core Complex Power Gating
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Solution Overview
Problem
The challenge of managing power consumption in multicore systems on a chip (SoC) is significant due to increased scale, particularly with more DRAM channels and CPU cores, leading to high costs and energy inefficiencies, especially in scenarios with varying utilization levels.
Innovation Solution
Implementing dynamic power management to power gate idle core complexes and adjust system directory capacity based on cache availability, reducing power consumption by modifying cache line tracking in the system directory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If system directory capacity is increased to track more cache lines, then cache coherence management capability is improved, but power consumption increases
Solution Approach 1:
The system directory capacity is made dynamic rather than static. The directory controller receives notifications about core complex power state transitions and adjusts the system directory capacity accordingly. When core complexes are power gated, the system directory capacity is reduced by deallocating tracking structures for those cores. When cores are awakened, capacity is reallocated. This dynamic adjustment allows the system to maintain adequate cache coherence management capability only when needed, reducing power consumption during low-utilization periods.
2Productivity
If more DRAM channels and CPU cores are integrated to scale up compute throughput, then processing capacity is improved, but power consumption and cost increase
Solution Approach 1:
The system is segmented into multiple independent core complexes, each with its own caches and directory tracking structures. This segmentation allows individual core complexes to be power gated independently without affecting others. The system directory is similarly segmented into tracking structures for individual cores, enabling granular power management where only the necessary directory entries are maintained active, reducing overall power consumption while maintaining high compute throughput capability when needed.
3Loss of energy
If system directory capacity is reduced to save power, then energy efficiency is improved, but cache coherence tracking capability deteriorates
Solution Approach 1:
A feedback mechanism is implemented where the directory controller receives notifications about core complex power state transitions. This feedback allows the system to dynamically adjust system directory capacity in response to actual workload conditions. When cores are active, full tracking capability is maintained; when cores are power gated, capacity is reduced. This feedback-driven approach ensures cache coherence tracking capability is maintained at appropriate levels without unnecessary energy consumption.
Data Source
AI summary
A system includes a core complex with multiple processor cores and multiple caches. The system also includes system directories that track cache residency in the caches of the core complex. Based at least in part on a power state transition of the core complex a system directory can adjust its capacity to track the cache residency.