System Latch Data Transfer for Valid-Only NAND Block Migration
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Solution Overview
Problem
Existing memory systems face issues with bandwidth consumption and latency due to the transfer of fragmented data, including both valid and invalid data, which results in invalid data being written to destination memory blocks, adversely impacting performance.
Innovation Solution
The use of a system latch to temporarily store valid data from source memory blocks in a sequential order, preventing invalid data from being written to destination memory blocks without relying on a controller, thereby maintaining bandwidth and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transferred from source memory blocks to destination memory blocks without validation, then transfer speed is improved, but invalid data is written to destination blocks causing data integrity issues
Solution Approach 1:
The patent applies preliminary action by validating data and determining its order in the source memory blocks before transferring to destination blocks. The controller identifies valid data and establishes the correct sequential order in advance, then transfers only the necessary valid data according to the determined order, preventing invalid data from being written while maintaining transfer efficiency.
2Productivity
If all data including fragmented invalid data is transferred, then bandwidth is consumed, but transfer completeness is maintained
Solution Approach 1:
The patent applies the taking out principle by extracting only the valid data from the source memory blocks and transferring exclusively that data to the destination blocks. The controller identifies and separates valid data from invalid fragmented data, transferring only the necessary valid portions according to their determined order, thereby avoiding bandwidth consumption on invalid data while ensuring transfer completeness.
3Measurement precision
If controller validation is performed for each data transfer, then data accuracy is improved, but latency increases
Solution Approach 1:
The patent applies preliminary action by performing data validation and order determination in advance before the actual transfer operation. The controller identifies valid data and establishes the correct sequential order beforehand, then executes the transfer in one efficient operation without per-data validation delays, thereby maintaining data accuracy while reducing transfer latency.
Data Source
AI summary
Methods, systems, and devices for transferring valid data using a system latch are described. The operations described herein may include sensing valid data across a first set of planes associated with a first set of memory blocks of a non-volatile memory system. In response to sensing the valid data, the valid data may be stored to a latch of the non-volatile memory system based on an order of sensing the valid data across the first set of planes. The valid data may be written across a second set of planes associated with a second set of memory blocks of the non-volatile memory system based on the order of sensing the valid data across the first set of planes. In some cases, writing the valid data from the latch may be based on determining that a threshold associated with a duration corresponding to sensing the valid data has been satisfied.