Multi-thread Safe System Level Modeling Simulation
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Solution Overview
Problem
SYSTEMC simulations face challenges in achieving reproducibility and multi-thread safety, especially when simulating target systems with multiple processor cores, due to data races and the need for synchronization that impacts performance.
Innovation Solution
Implementing deferred execution, direct memory interface access in exclusive execution mode, and guarded memory access to ensure reproducibility and multi-thread safety by managing shared resource access and memory interactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-threaded execution is used to speed up SYSTEMC simulation, then simulation speed is improved, but multi-thread safety and reproducibility are compromised due to data races and synchronization issues
Solution Approach 1:
The patent applies preliminary action by detecting shared resource accesses during the parallel execution phase and deferring them to a sequential execution phase. This allows the system to prepare and identify potential data race conditions before they can cause reproducibility issues, enabling multi-threaded execution to proceed safely while maintaining simulation speed improvements.
Solution Approach 2:
The patent segments the execution process into distinct phases: a parallel execution phase for speed-critical operations and a sequential execution phase for shared resource access operations. This segmentation allows the system to maximize productivity during parallel execution while ensuring reproducibility during sequential execution of deferred operations, effectively resolving the contradiction between speed and reliability.
2Reliability
If synchronization elements like OS mutexes are used to ensure multi-thread safety, then data races are prevented, but simulation performance deteriorates due to overhead
Solution Approach 1:
The patent extracts the synchronization mechanism from the traditional approach of using OS mutexes during parallel execution. Instead, it identifies shared resource accesses and defers them to a sequential phase, eliminating the need for heavy-weight synchronization primitives during the performance-critical parallel execution phase while still ensuring multi-thread safety.
Solution Approach 2:
The patent introduces a deferred execution mechanism as an intermediary between parallel execution and shared resource access. This intermediary captures shared resource access operations during parallel execution and processes them sequentially, acting as a mediator that ensures multi-thread safety without the performance overhead of traditional synchronization elements.
3Reliability
If conventional synchronization approaches are used, then multi-thread safety is achieved, but IEEE Std. 1666-2011 compliance regarding reproducible process execution order is not satisfied
Solution Approach 1:
The patent applies dynamics by making the execution mode adaptive based on the operation type. Parallel execution is used for operations that do not access shared resources, while sequential execution is dynamically applied to deferred shared resource access operations. This dynamic approach ensures both multi-thread safety and compliance with IEEE Std. 1666-2011 requirements for reproducible process execution order.
Solution Approach 2:
The patent changes the execution parameter from always-parallel to conditionally-sequential for deferred operations. By modifying the execution mode parameter based on whether an operation accesses shared resources, the system achieves both multi-thread safety and IEEE standard compliance, as the sequential execution of deferred operations ensures reproducible process execution order.
Data Source
AI summary
Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.