System-Level Packaging Integrating Chips and Passive Devices
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Solution Overview
Problem
Conventional wafer level packaging technologies are limited to single-chip functions and face challenges in integrating passive devices like capacitors, resistors, and inductors, which are necessary for whole-system functions, leading to increased interference and complexity in semiconductor packaging.
Innovation Solution
A packaging structure that integrates chips and passive devices on a carrier board with a sealing material layer, where the adhesive layer is designed to match the shape and position of the devices, and the sealing material layer is filled between them, reducing stress and distortion, and includes a metal re-wiring layer and protective film for electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional wafer level packaging technology is used to package only single chips, then the packaging process is simple, but the system functionality is incomplete and additional passive devices are required separately
Solution Approach 1:
The patent merges chips and passive devices (capacitors, resistors, inductors) into a single packaging structure by forming a sealing material layer that encapsulates both active and passive components together on the carrier board,实现系统级封装
Solution Approach 2:
The packaging structure is designed to accommodate multiple types of components (chips and various passive devices) with different functions within a single sealed unit, making the packaging structure universal for complete system functionality
2Volume of moving object
If chips and passive devices are packaged separately, then the packaging process is simple, but the overall size and weight increase
Solution Approach 1:
The patent nests passive devices and chips within the same sealing material layer, with components arranged in a compact configuration where smaller components are positioned around and between larger chips, maximizing space utilization
Solution Approach 2:
The patent utilizes the vertical dimension by forming a thick sealing material layer that completely encapsulates components arranged in two dimensions on the carrier board, creating a three-dimensional integrated packaging structure
3Ease of manufacture
If adhesive layer covers the entire carrier board surface, then device attachment is easy, but stress distribution is poor causing warping
Solution Approach 1:
The patent segments the continuous adhesive layer into discrete adhesive blocks positioned only at specific locations where chips and passive devices need to be attached to the carrier board, reducing overall adhesive material and stress
Solution Approach 2:
The patent applies adhesive locally only where needed for device attachment rather than uniformly across the entire carrier board surface, optimizing both attachment effectiveness and stress distribution
4Adaptability or versatility
If passive devices are integrated into the packaging, then whole-system functions are achieved, but interference between components increases
Solution Approach 1:
The patent extracts passive devices from separate packaging and integrates them within the same sealing material layer as chips, but positions them strategically to minimize electromagnetic and signal interference while maintaining compact form factor
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-density, high-integrity packaging with whole-system functions, reducing interference and improving the quality of semiconductor products by integrating chips and passive devices, making the packaging lighter, thinner, and more reliable.
Implementation Method 1
an adhesive layer on a surface of the carrier board, chips and passive devices attached to the adhesive layer
Implementation Method 2
a sealing material layer formed on a surface of the carrier board to which the chips and the passive devices are attached
Data Source
AI summary
The present invention relates a packaging structure including: a carrier board and a cementing layer on the surface of the carrier board; chips and passive devices having functional side thereof attached to the cementing layer; and a sealing material layer for packaging and curing, the sealing material being formed on the carrier board on the side attached to the chips and the passive devices. The present invention integrates chips and passive devices and then packages the chips and the passive devices together, and is therefore a packaged product having not single-chip functionality but integrated-system functionality. The present invention is highly integrated, reduces interfering factors such as system-internal electric resistance and inductance, and accommodates growing demand for lighter, thinner, shorter, and smaller semiconductor packaging.