System-Level Packaging Structure for High Integration
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Solution Overview
Problem
Current IC packaging technologies face challenges in achieving high integration, miniaturization, and reliability, particularly at the system level, as they struggle to meet the increasing demands for lighter, thinner, and more functional electronic products.
Innovation Solution
A system-level packaging method and structure that involves a packaging substrate with two package layers, each comprising a mounting layer, a sealant layer, and a wiring layer, along with a top sealant layer and connection balls on the second surface, to enhance integration and reliability through precise layer formation and wiring arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional packaging substrate structures are used, then manufacturing simplicity is maintained, but system-level packaging integration degree remains insufficient
Solution Approach 1:
The packaging substrate is divided into multiple functional layers including a substrate layer, first package layer with mounting layer/sealant layer/wiring layer, second package layer with similar structure, and top sealant layer. This segmentation allows each layer to perform specific functions while achieving high integration degree through modular stacking architecture
Solution Approach 2:
The patent transitions from planar packaging to three-dimensional stacked packaging by adding vertical layers (mounting layer, sealant layer, wiring layer) stacked on top of each other. This dimensional change enables multiple devices to be integrated vertically, significantly increasing packaging integration degree while maintaining manufacturing feasibility through layer-by-layer fabrication
2Device complexity
If IC chip size decreases and integration degree increases, then device functionality improves, but packaging reliability requirements become more stringent
Solution Approach 1:
Sealant layers are placed between the mounting layer and substrate, and between wiring layers, to provide protective cushioning against mechanical stress, thermal expansion mismatches, and environmental damage. This beforehand cushioning protects the miniaturized IC chips and their delicate interconnections, maintaining packaging reliability despite increased integration and reduced chip size
Solution Approach 2:
The packaging substrate employs composite material structure combining substrate material (for mechanical support), sealant material (for protection and insulation), and conductive material (for electrical connections). This composite approach ensures that each material contributes its optimal properties, maintaining overall packaging reliability while supporting high integration of miniaturized components
Data Source
AI summary
A system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least two package layers on the first functional surface of the packaging substrate, wherein each package layer is formed by subsequently forming a mounting layer, a sealant layer, and a wiring layer. Further, the method includes forming a top sealant layer and planting connection balls on the second functional surface of the packaging substrate.