Generalized System Stutter for Power Management

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Solution Overview

Problem

Existing power management systems face challenges in achieving energy efficiency due to high latency associated with transitioning between power states, particularly in systems with multiple I/O agents having distinct timing requirements, where redesigning these agents is costly and risky.

Innovation Solution

A generalized system stutter method that blocks requests from bus masters during a low power state and services them during an active state, using a centralized stutter unit with blockers to manage memory access requests and cluster them with display system requests, thereby optimizing energy efficiency without requiring redesign of I/O agents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the system enters low power state to reduce energy consumption, then energy efficiency is improved, but latency increases when transitioning back to active state

Engineering Contradiction:
Improveenergy efficiencyVSAvoidtransition latency
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The system performs preliminary actions by pre-fetching data into FIFO buffers before entering low power state, and by proactively exiting low power state when buffers approach critical watermarks. This preliminary preparation ensures that when the system needs to access memory during low power state, the data is already available or will be available immediately, thus reducing the effective latency impact while maintaining energy efficiency.

Inventive Principle:
Principle #10Preliminary action

2Use of energy by moving object

If multiple I/O agents are redesigned to support stutter requirements, then energy efficiency is improved, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improveenergy efficiencyVSAvoidsystem complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent introduces a centralized stutter unit as an intermediary component that mediates between multiple I/O agents and the memory system. This stutter unit consolidates the stutter management functionality in a single location, allowing all I/O agents to benefit from energy efficiency improvements without requiring individual redesign. The stutter unit handles buffer management, watermark monitoring, and coordinated memory access clustering, thereby reducing overall system complexity while achieving the energy efficiency benefits.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Use of energy by moving object

If memory access requests are clustered to enable low power state, then energy efficiency is improved, but timing requirements may not be met

Engineering Contradiction:
Improveenergy efficiencyVSAvoidtiming requirement compliance
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The system implements feedback mechanisms through watermark monitoring in FIFO buffers. When buffer levels approach critical watermarks, the system receives feedback and proactively exits low power state to refill buffers, ensuring that timing requirements are met. This feedback-driven approach allows the system to dynamically adjust its power state transitions based on actual buffer status, maintaining reliability while maximizing energy efficiency opportunities.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS7849342B2Method and system for implementing generalized system stutter
Publication Date: 2010.12.07 NVIDIA CORP
  • US7849342B2 patent drawing
  • US7849342B2 patent drawing
  • US7849342B2 patent drawing

AI summary

A method and system for implementing a generalized system stutter are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of blocking a first request received from a first of a plurality of bus masters during a low power state of a computing device for as long as permissible by the timing requirements of the computing device, wherein the first request is capable of triggering the computing device to transition out of the low power state, and during an active state of the computing device, servicing the first request along with other pending requests from the rest of the plurality of bus masters before the computing device transitions back to the low power state.