System-on-Wafer Chiplet Structure Without TSV Yield Loss
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Solution Overview
Problem
Current system-on-wafer (SoW) technologies face challenges in yield and reliability due to the reliance on single process nodes and high-density Through Silicon Via (TSV) interconnects, which can lead to system failure and reliability issues when defects occur.
Innovation Solution
A SoW structure and fabrication method that integrates a wafer substrate, integrated chiplet, system configuration board, and thermal module, utilizing a re-distributed layer, wafer micro bump array, copper pillar array, and C2W bonding process to enhance connectivity and reliability, with a thermal module for cooling, allowing for heterogeneous chiplet integration and improved electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high-density TSV interconnect technology is used to assemble multiple die together, then system integration capability is improved, but yield and reliability deteriorate due to defect propagation and process challenges
Solution Approach 1:
The patent segments the monolithic SoW structure into multiple independent chiplets (compute chiplet, memory chiplet, I/O chiplet) that can be separately manufactured, tested, and assembled. This segmentation allows individual chiplets to be produced on different process nodes and assembled into a functional system, improving both integration capability and reliability by isolating defects to individual chiplets rather than failing the entire system.
Solution Approach 2:
The patent introduces an intermediary substrate as a mediator between chiplets and the final package. This intermediary substrate provides a platform for assembling multiple chiplets with different process nodes and technologies, enabling flexible system integration while maintaining reliability through the modular assembly approach rather than direct monolithic integration.
2Ease of manufacture
If a single process node is used to prepare multiple die on wafer, then manufacturing simplicity is improved, but yield deteriorates because a single defect causes entire system failure
Solution Approach 1:
The patent divides the system into multiple chiplets that can be manufactured on different process nodes (e.g., 5nm for compute, 10nm for memory, 180nm for I/O). Each chiplet is independently manufactured and tested, so a defect in one chiplet does not affect the others. This segmentation maintains manufacturing simplicity through standardized assembly processes while dramatically improving yield by isolating failures to individual chiplets.
3Adaptability or versatility
If heterogeneous chiplet integration is implemented, then system performance and flexibility are improved, but device complexity increases
Solution Approach 1:
The patent employs a universal intermediary substrate design that can accommodate multiple types of chiplets (compute, memory, I/O) with different process nodes and functionalities. The substrate provides standardized interconnect interfaces and routing that work with all chiplet types, enabling heterogeneous integration without proportionally increasing complexity. This universal platform approach allows flexible system configuration while maintaining manageable device complexity through standardized interfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution significantly improves the yield and reliability of SoW by enabling high-density integration and flexible chiplet configurations, addressing the limitations of traditional TSV technologies and enabling more robust and efficient system performance.
Implementation Method 1
The wafer substrate and the system configuration board are bonded through the copper pillar array and the pad on system configuration board
Implementation Method 2
The thermal module is attached to the backside of the wafer substrate
Data Source
AI summary
A system-on-wafer structure and a fabrication method. The structure includes a wafer substrate, an integrated chiplet, a system configuration board and a thermal module. The wafer substrate and the integrated chiplet are bonded through a wafer micro bump array and a chiplet micro bump array. The wafer substrate and the system configuration board are bonded through a copper pillar array on wafer substrate topside and a pad on system configuration board backside. A molding layer is provided between the wafer substrate and the system configuration board, and is configured to mold the wafer substrate, the integrated chiplet and the copper pillar array. Integrated chiplet are electrically connected to each other through a re-distributed layer in wafer substrate. The integrated chiplet is electrically connected to the system configuration board through the re-distributed layer and the copper pillar array. The thermal module is attached to the backside of the wafer substrate.