Circular Buffer Bit Interleaving for High Code Rate Matching

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Solution Overview

Problem

Conventional rate matching techniques in wireless communication systems are complex and primarily intended for transport channel multiplexing, making them inefficient for handling high code rate conditions where turbo-coded data exceeds transmission capacity.

Innovation Solution

The implementation of circular buffer based rate matching, which separates and interleaves systematic, parity 1, and parity 2 bits, preferentially transmitting systematic bits and then parity bits, allowing for efficient data transfer by inserting these bits into a circular buffer for transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional rate matching techniques are used, then transport channel multiplexing is supported, but the complexity of the system increases and performance under high code rate conditions deteriorates

Engineering Contradiction:
Improvetransport channel multiplexing supportVSAvoidrate matching complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the coded bits into three distinct groups (systematic bits, first parity bits, second parity bits) and processes each group separately through circular buffering and interleaving operations. This segmentation simplifies the overall rate matching process while maintaining support for transport channel multiplexing by applying different circular shift values to different bit groups.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If conventional rate matching techniques are used, then transport channel multiplexing is supported, but performance under high code rate conditions deteriorates

Engineering Contradiction:
Improvetransport channel multiplexing supportVSAvoidperformance under high code rate conditions
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies local quality by treating different bit groups (systematic bits, first parity bits, second parity bits) with different circular shift values during the interleaving process. This allows optimization for high code rate conditions where systematic bits are critical, while still maintaining transport channel multiplexing capability through the structured approach.

Inventive Principle:
Principle #3Local quality

3Reliability

If systematic bits are preferentially transmitted, then performance under high code rate conditions improves, but the complexity of rate matching increases

Engineering Contradiction:
Improveperformance under high code rate conditionsVSAvoidrate matching complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary action by separating bits into groups and applying circular buffering with different shift values before transmission. This preliminary organization preferentially positions systematic bits for transmission while maintaining a structured process that does not significantly increase complexity compared to conventional techniques.

Inventive Principle:
Principle #10Preliminary action

4Productivity

If bits are punctured to match channel capacity, then the number of transmitted bits matches channel capability, but loss of information increases

Engineering Contradiction:
Improvechannel utilizationVSAvoidbit loss from puncturing
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The patent changes parameters by applying different circular shift values to different bit groups during interleaving. This allows the system to match channel capacity through controlled puncturing while minimizing information loss by preferentially retaining systematic bits and using parity bits as the puncturing target, thereby optimizing channel utilization.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20090049359A1Circular buffer based rate matching
Publication Date: 2009.02.19 QUALCOMM INC
  • US20090049359A1 patent drawing
  • US20090049359A1 patent drawing
  • US20090049359A1 patent drawing

AI summary

Systems and methodologies are described that facilitate employing circular buffer based rate matching. Encoded block(s) that include systematic, parity 1, and parity 2 bits can be generated using turbo code. Bit type can be identified to separate bits into distinct groups. Systematic bits can be interleaved together to generate a randomized sequence of systematic bits, parity 1 bits can be interleaved together to yield a randomized sequence of parity 1 bits, and parity 2 bits can be interleaved together to output a randomized sequence of parity 2 bits. The randomized sequences of parity 1 bits and parity 2 bits can be interlaced together in an alternating manner. The randomized sequence of systematic bits can be inserted into a circular buffer, and upon inserting the entire sequence, the interlaced parity bits can be inserted into the circular buffer (e.g., until reaching capacity). Bits inserted into the circular buffer are transmitted.