SystemVerilog Real Nettype for Mixed-Signal Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current SystemVerilog language lacks effective support for real number modeling and bi-directional communication, limiting its ability to accurately model analog and mixed-signal behaviors, especially in chip-level functional verification of SoCs with growing analog circuitry, where isolated digital and analog verification are insufficient.
Innovation Solution
The implementation of built-in nettypes with real data types and resolution functions in SystemVerilog, along with support for migrating Verilog-AMS models, enables real number modeling and compatibility with VHDL, allowing for bi-directional communication and mixed-signal design verification through net coercion and connect module insertion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SystemVerilog is used for digital circuit modeling, then digital verification capability is improved, but analog/mixed-signal modeling capability deteriorates
Solution Approach 1:
The patent extends SystemVerilog to serve both digital and analog/mixed-signal verification functions. By introducing real signal data types, continuous assignment statements, and analog behavioral modeling constructs, SystemVerilog becomes a universal language capable of verifying both digital logic circuits and analog/mixed-signal circuits within a single HDL framework, eliminating the need for separate verification environments.
Solution Approach 2:
The patent merges previously separate digital and analog verification methodologies into a unified SystemVerilog-based verification platform. By integrating real number modeling, continuous time simulation, and analog device modeling capabilities directly into SystemVerilog, the toolchain combines the strengths of digital HDL verification with analog circuit analysis in a single cohesive system.
2Adaptability or versatility
If real number modeling is added to SystemVerilog, then analog behavioral modeling capability is improved, but language complexity increases
Solution Approach 1:
The patent introduces analog modeling capabilities locally within SystemVerilog through specific constructs such as real signal data types, continuous assignment statements, and analog behavioral modeling blocks. These analog features are integrated at specific locations in the language syntax rather than requiring a complete language overhaul, allowing digital and analog modeling to coexist with minimal interference between the two paradigms.
Solution Approach 2:
The patent segments the verification process into distinct digital and analog modeling regions within SystemVerilog code. By using separate data types (logic types for digital, real types for analog), separate assignment mechanisms (discrete event for digital, continuous for analog), and separate simulation domains, the language divides complex mixed-signal verification into manageable segments that can be handled independently yet integrated seamlessly.
3Measurement precision
If bi-directional communication support is implemented, then mixed-signal verification accuracy is improved, but implementation complexity increases
Solution Approach 1:
The patent introduces intermediary constructs such as real signal ports, buffer elements, and conversion modules that facilitate bi-directional communication between digital and analog domains. These intermediaries act as translators and adapters, enabling seamless data exchange between discrete event driven digital verification and continuous time analog simulation without requiring complex custom integration logic.
Data Source
AI summary
Some embodiments provide support for real number modeling in SystemVerilog by defining built-in nettypes with real data type and resolution functions natively in SystemVerilog and allow a simple path for porting Verilog-AMS wreal modeling to SystemVerilog modeling. Some embodiments provide support for incompatible nettypes and for net coercion in SystemVerilog. Some embodiments provide support for SystemVerilog reals net connecting to electrical nets and support for SystemVerilog real signals connecting to Verilog-AMS wreal signals. Some embodiments combine the strengths of Verilog-AMS and SystemVerilog languages to build a solution for value conversion between incompatible nets and an effective way to configure, simulate, or verify mixed-signal designs that are written in SystemVerilog language.