Systolic Array Checksum Circuit for Real-Time Error Detection
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Solution Overview
Problem
Current systolic arrays lack efficient error detection mechanisms that can operate without pre-processing inputs or post-processing outputs, making it difficult to rapidly identify hardware faults and errors during critical tasks like machine learning operations, especially when processing matrices.
Innovation Solution
A computation unit with integrated checksum circuits that generate and compare checksums within the systolic array, allowing for real-time error detection and correction during matrix multiplication, without the need for pre-processing inputs or post-processing outputs, and can operate at reduced voltage levels to improve energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If checksum circuits are integrated into the systolic array for real-time error detection, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the checksum computation functionality directly into the systolic array processing elements. Each processing element includes both the computational unit and the checksum circuit, combining data processing and error detection functions into a single integrated structure. This eliminates the need for separate checksum generation and verification units, thereby improving reliability while controlling the increase in device complexity.
Solution Approach 2:
The processing elements in the systolic array are designed with multi-functionality, serving both as computational units for matrix operations and as checksum generators for error detection. The same hardware resources perform multiple functions: data processing, checksum computation, and error detection, reducing the overall system complexity compared to having dedicated separate circuits for each function.
2Reliability
If checksums are computed and compared in real-time during matrix multiplication, then reliability is improved, but use of energy increases
Solution Approach 1:
The checksum computation is performed continuously alongside the matrix multiplication operations without interrupting the computational flow. The checksum circuits operate in parallel with the processing elements, computing checksums during the same time steps that data processing occurs. This continuous operation eliminates the need for separate pre-processing or post-processing phases, maintaining useful action continuity while distributing energy consumption across the computation timeline.
Solution Approach 2:
The systolic array performs self-verification through integrated checksum circuits that automatically detect errors during computation. The error detection mechanism serves the computational process itself rather than requiring external verification systems. This self-service approach eliminates the need for separate verification passes or additional processing stages, reducing overall energy consumption while maintaining high reliability.
3Productivity
If error detection is implemented without pre-processing inputs or post-processing outputs, then productivity is improved, but measurement precision requirements increase
Solution Approach 1:
The checksum computation is initiated simultaneously with the input data loading into the systolic array, rather than performing pre-processing before computation. The checksum circuits begin generating checksums as data enters the processing elements, eliminating idle time and ensuring that checksums are ready for verification without delaying the computational throughput. This preliminary action approach maintains high productivity while ensuring accurate measurement through concurrent computation.
4Use of energy by moving object
If the systolic array operates at reduced voltage levels for energy efficiency, then use of energy is reduced, but reliability decreases due to timing violations
Solution Approach 1:
The integrated checksum circuits provide real-time feedback on computational accuracy to the control logic. When operating at reduced voltage levels, the feedback mechanism monitors for timing violations and errors, enabling the system to detect and correct issues that arise from voltage reduction. This feedback loop allows the systolic array to operate efficiently at lower voltages while maintaining reliability through active error detection and correction.
Data Source
AI summary
Aspects of the disclosure are directed to a computation unit implementing a systolic array and configured for detecting errors while processing data on the systolic array. Checksum circuit in communication with a systolic array is configured to compute checksums and perform error detection while the systolic array processes input data. Instead of pre-generating checksums in input matrices, input matrices can be directly fed into the systolic array through the checksum circuit. On the output side, the checksum circuit can generate and compare checksums with checksums in an output matrix generated by the systolic array. Error checking the operations to generate the output matrix can be performed without delaying the operations of the systolic array, and without preprocessing the input matrices.