Systolic Array Clock Skew via Pipelined Registers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Systolic arrays face limitations in processing speed and power efficiency due to constraints in clock signal design, particularly along the critical path, which affects the performance of operations in machine learning applications like neural networks.
Innovation Solution
Implementing techniques to increase positive clock skew along the critical path of systolic arrays through the use of pipelined registers, optimized clock tree synthesis, and strategic clock signal routing, including center main trunks and reverse X-bus direction clock branches, to synchronize processing elements and enhance performance attributes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional clock signal design is used in systolic arrays, then device complexity is reduced, but processing speed deteriorates due to constraints along the critical path
Solution Approach 1:
The clock tree is segmented into multiple independent branches (e.g., X-bus direction main trunk, reverse X-bus direction main trunk, Y-bus direction main trunk) that can be optimized separately. Each branch serves specific regions of the systolic array, allowing independent timing optimization without affecting the entire clock distribution network.
Solution Approach 2:
Different clock skew values are applied to different regions of the systolic array based on their specific timing requirements. The patent implements region-specific clock tree synthesis where critical paths receive optimized skew compensation while non-critical regions use standard clock distribution.
2Speed
If positive clock skew is increased along the critical path, then processing speed improves, but power consumption increases due to enhanced clock signaling requirements
Solution Approach 1:
Clock skew compensation is applied selectively only to critical paths that require it, rather than uniformly across the entire systolic array. The patent identifies specific critical regions and applies enhanced clock tree synthesis only where timing constraints demand positive skew, reducing overall power consumption compared to a universal approach.
3Productivity
If optimized clock tree synthesis is implemented, then processing speed improves, but device complexity increases due to additional clock routing structures
Solution Approach 1:
The clock tree structure employs asymmetric routing where different main trunks (X-bus direction, reverse X-bus direction, Y-bus direction) have different topologies optimized for their respective data flow directions. This asymmetric design allows efficient clock distribution matching the asymmetric data movement patterns in systolic arrays without requiring symmetric complexity.
Data Source
AI summary
Clock skew may be increased along a critical path of a systolic array. Pipelined registers may be added between a bus that provides input data signals to a systolic array and between a bus that receives output data signals from the systolic array. Skew circuitry for the pipelined registers may be implemented to delay a clock signal to the pipelined registries to allow a clock skew accumulated along a critical path of the systolic array to exceed a single clock cycle.