Systolic Array Processor Core Matrix with Dynamic Multiplexer Routing
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Solution Overview
Problem
Existing processors specialized for convolutional operations in deep learning often face inefficiencies due to systolic arrays of fixed sizes, which can lead to reduced processing efficiency when handling large amounts of data, and require data division and multiple loading cycles.
Innovation Solution
A processor architecture featuring multiple processing cores with arithmetic unit arrays, each equipped with first and second memories, and multiplexers to connect input data and weight data from local memories or adjacent processing cores, allowing for dynamic reconfiguration of the systolic array and efficient data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed-size systolic array is used, then the processor structure is simple, but processing efficiency decreases when handling large amounts of data
Solution Approach 1:
The patent implements dynamic reconfiguration of the systolic array by allowing processing cores to be dynamically added or removed based on data size requirements. The multiplexer dynamically switches between different input sources (local memory or adjacent processing core) depending on the operational mode, enabling the system to adapt its structure to match the processing workload and maintain high efficiency across varying data volumes.
2Productivity
If data is divided and loaded multiple times, then the fixed-size systolic array can process data, but processing efficiency is reduced
Solution Approach 1:
The patent implements preliminary action by pre-loading data into local memories of multiple processing cores before the actual convolution operation begins. This allows the systolic array to receive data continuously from multiple sources simultaneously, eliminating the need for repeated data loading cycles and maintaining continuous processing flow, thereby reducing time loss and improving overall processing efficiency.
3Quantity of substance
If input data is output from buffer sequentially, then memory usage is optimized, but additional storage is required when stride value changes
Solution Approach 1:
The patent implements universality by designing the multiplexer to handle multiple input sources (local memory and adjacent processing core output) and multiple output destinations. This multi-functional design allows the same hardware structure to accommodate different stride values and data access patterns without requiring additional storage, as the multiplexer can dynamically route data flows to match various processing requirements.
Data Source
AI summary
A processor having a systolic array that can perform operations efficiently is provided. The processor includes multiple processing cores aligned in a matrix, and each of the processing cores includes an arithmetic unit array including multiple arithmetic units that can form a systolic array. Each of the processing cores includes a first memory that stores first data, a second memory that stores second data, a first multiplexer that connects a first input for receiving the first data at the arithmetic unit array to an output of the first memory in the processing core or an output of the arithmetic unit array in an adjacent processing core, and a second multiplexer that connects a second input for receiving the second data at the arithmetic unit array to an output of the second memory in the processing core or an output of the arithmetic unit array in an adjacent processing core.