Systolic Array Dispatch for Concurrent Reconfiguration Control
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Solution Overview
Problem
Conventional parallel processing units face inefficiencies due to the inability to reconfigure systolic arrays concurrently with executing instructions, leading to increased latency and overhead when conflicts arise with previously dispatched kernels.
Innovation Solution
Implement a hierarchical set of controllers to manage and reconfigure systolic arrays concurrently with parallel processors by inspecting packets and determining whether reconfiguration conflicts exist, allowing simultaneous execution and reconfiguration when possible, and serial execution when conflicts are detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional parallel processing units execute instructions sequentially without concurrent reconfiguration, then system simplicity is maintained, but reconfiguration latency increases and processing time extends
Solution Approach 1:
The patent divides the control system into a hierarchical structure with multiple levels of controllers. The first level includes a command processor that manages high-level instruction dispatch, while the second level includes individual controllers for each compute unit that handle local reconfiguration tasks. This segmentation enables concurrent reconfiguration operations at different levels without creating conflicts, allowing the systolic array to be reconfigured while instructions are executing without increasing overall system complexity.
Solution Approach 2:
The command processor performs preliminary actions by inspecting packets before they reach the systolic array and determining whether reconfiguration is needed. The hierarchical controllers prepare reconfiguration commands in advance and route them to the appropriate compute units. This preliminary action allows reconfiguration operations to overlap with instruction execution, reducing reconfiguration latency while maintaining system simplicity through proactive rather than reactive control.
2Productivity
If the systolic array is reconfigured concurrently with executing instructions, then processing throughput improves, but conflicts with previously dispatched kernels may arise
Solution Approach 1:
The hierarchical controller system implements feedback mechanisms where controllers at the second level continuously monitor the execution state of instructions and the configuration state of the systolic array. When conflicts are detected between concurrently executing instructions and reconfiguration operations, the system receives feedback about the conflict condition and adjusts the reconfiguration timing or routing to resolve the conflict, ensuring execution correctness while maintaining high throughput.
Solution Approach 2:
The patent introduces dynamic control where the reconfiguration process is not fixed but adapts based on the current execution state. The command processor dynamically determines whether to allow concurrent reconfiguration by inspecting packet contents and checking for conflicts. The hierarchical controllers dynamically route reconfiguration commands to appropriate compute units based on real-time system state, enabling the system to maximize productivity while ensuring reliability through adaptive decision-making.
3Loss of time
If a hierarchical controller system is implemented to manage concurrent reconfiguration, then reconfiguration latency is reduced, but control complexity increases
Solution Approach 1:
The control system is segmented into multiple hierarchical levels with distinct responsibilities. The command processor handles high-level dispatch decisions and packet inspection, while individual controllers at the second level handle local reconfiguration tasks for specific compute units. This segmentation distributes the control burden and enables concurrent operations without requiring a single complex monolithic controller, thus reducing overall reconfiguration time while keeping each controller level relatively simple.
Solution Approach 2:
The hierarchical controllers act as intermediaries between the command processor and the compute units. These intermediary controllers receive reconfiguration commands from the command processor, inspect them for conflicts with currently executing instructions, and route them to the appropriate compute units. This intermediary layer simplifies the overall control architecture by breaking down complex coordination tasks into smaller, manageable steps, reducing reconfiguration latency without proportionally increasing control complexity.
Data Source
AI summary
A command processor dispatches instructions to a processing unit and a systolic array. The command processor receives a packet including instructions for execution on the systolic array. In response to determining that reconfiguration of the systolic array is to be performed in order to process the instructions, the command processor determines whether a previously dispatched packet is executing on the systolic array. The command processor dispatches reconfiguration instructions for execution concurrently with the processing unit executing the previously dispatched packet in response to determining that there is no conflict between the reconfiguration instructions and a current configuration used by the previously dispatched packet. If a conflict exists between the reconfiguration instructions and the current reconfiguration, the command processor waits for an acknowledgment indicating that execution of the previously dispatched packet is complete and dispatches the reconfiguration instructions.