Systolic Array Hardware for Double Precision Matrix Multiplication
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Solution Overview
Problem
Current graphics processing units (GPUs) face limitations in efficiently processing graphics and machine-learning operations due to the need for increased precision and parallel processing capabilities, particularly in handling complex computations like matrix multiplication and neural network training, which are not adequately supported by existing SIMT architectures.
Innovation Solution
The implementation of a general-purpose graphics processing unit (GPU) with enhanced systolic array hardware and double-precision floating-point support, including dedicated MAC units and a systolic array architecture, enables higher precision calculations and improved parallel processing for graphics and machine-learning operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SIMT architecture is used to maximize parallel processing, then processing efficiency is improved, but precision for complex computations deteriorates
Solution Approach 1:
The patent segments the processing architecture into two distinct pathways: a SIMT execution path for general parallel graphics operations and a dedicated systolic array path for high-precision matrix multiplication. This segmentation allows each pathway to be optimized for its specific function, maintaining both parallel processing efficiency and computational precision simultaneously.
Solution Approach 2:
The GPU architecture is designed with multi-functionality to handle both graphics processing and machine learning workloads. The unified memory space and instruction set architecture allow the same hardware to execute both SIMT-based graphics operations and systolic array-based ML computations, providing universal support for diverse computational needs while maintaining precision where required.
2Productivity
If fixed function computational units are used, then graphics processing is optimized, but adaptability to machine-learning operations deteriorates
Solution Approach 1:
The patent implements a universal GPU architecture that supports both traditional graphics operations and machine learning computations through a unified instruction set and memory architecture. The ability to execute both SIMT-based graphics shaders and systolic array-based ML algorithms on the same hardware demonstrates multi-functionality, eliminating the need for separate dedicated hardware for different workloads.
Solution Approach 2:
The architecture dynamically adapts its execution model based on the workload type. For graphics operations, it employs SIMT execution with thread bundles optimized for rendering pipelines. For machine learning tasks, it dynamically switches to systolic array execution patterns, allowing the same hardware to change its operational characteristics according to the computational requirements.
3Speed
If single precision processing is used, then processing speed is improved, but calculation accuracy deteriorates
Solution Approach 1:
The patent applies different precision levels to different computational pathways based on local quality requirements. The systolic array pathway for matrix multiplication uses double precision floating-point arithmetic to maintain high calculation accuracy for machine learning operations, while the SIMT pathway can utilize single precision for graphics operations where maximum speed is prioritized. This localized precision approach optimizes both speed and accuracy where needed.
Data Source
AI summary
An apparatus to facilitate hardware enhancements for double precision systolic support is disclosed. The apparatus includes matrix acceleration hardware having double-precision (DP) matrix multiplication circuitry including a multiplier circuits to multiply pairs of input source operands in a DP floating-point format; adders to receive multiplier outputs from the multiplier circuits and accumulate the multiplier outputs in a high precision intermediate format; an accumulator circuit to accumulate adder outputs from the adders with at least one of a third global source operand on a first pass of the DP matrix multiplication circuitry or an intermediate result from the first pass on a second pass of the DP matrix multiplication circuitry, wherein the accumulator circuit to generate an accumulator output in the high precision intermediate format; and a down conversion and rounding circuit to down convert and round an output of the second pass as final result in the DP floating-point format.