Systolic Array Fault Bypassing for Yield Improvement

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Solution Overview

Problem

The low production yield of systolic array devices due to the need to discard entire chips when faults are detected in processing elements during manufacturing, as the processing of input and output features is lock-step and any fault in one element requires discarding the entire chip.

Innovation Solution

A systolic array device configuration that allows for data bypassing in processing units with faults, utilizing preliminary processing units to maintain operation and improve yield, where transfer parts, such as multiplexers, manage data flow and results around faulty units, enabling continued functionality even with faulty main processing units.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fault is detected in any processing element during manufacturing, then the entire chip must be discarded to ensure processing reliability, but this results in low production yield

Engineering Contradiction:
Improveprocessing reliabilityVSAvoidproduction yield
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The systolic array is divided into multiple processing units, each consisting of a processing element and transfer parts. This segmentation allows the system to isolate faults to specific processing units rather than requiring discarding of the entire chip, thereby maintaining processing reliability while improving production yield through selective bypassing of faulty segments.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Preliminary processing units are configured in advance to serve as backup units. When a fault is detected in a main processing unit, the system can switch to using the preliminary processing units, ensuring processing reliability is maintained without discarding the entire chip, thus improving production yield.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the entire chip is discarded when a fault is detected, then processing reliability is maintained, but manufacturing cost increases due to low production yield

Engineering Contradiction:
Improveprocessing reliabilityVSAvoidchip waste
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

Preliminary processing units are prepared in advance as backup resources. When faults occur in main processing units, these preliminary units provide a cushion that allows the system to continue operating without discarding the entire chip, thereby maintaining processing reliability while reducing chip waste and improving manufacturing efficiency.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Productivity

If data bypassing is implemented around faulty processing units, then production yield is improved, but device complexity increases due to additional transfer parts and control logic

Engineering Contradiction:
Improveproduction yieldVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The transfer parts are designed with multi-functionality, serving both normal data transfer between processing units and bypassing faulty units. This universal design allows the same hardware components to perform multiple functions, reducing the need for additional dedicated bypassing hardware and thereby limiting the increase in device complexity while still improving production yield.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12019582B2Systolic array device
Publication Date: 2024.06.25 REBELLIONS INC
  • US12019582B2 patent drawing
  • US12019582B2 patent drawing
  • US12019582B2 patent drawing

AI summary

A systolic array device according an embodiment includes a plurality of processing units arranged in a matrix form of M by N (M and N are natural numbers). Each of the processing units includes: a processing element configured to perform a predetermined processing based on data received from a processing unit arranged adjacent to one side of the corresponding processing unit to output a result thereof; and a transfer part configured to perform one of an operation of transferring the received data to another processing unit arranged adjacent to the other side of the corresponding processing unit and an operation of transferring the result.