On-Chip Systolic Array for Faster FHE Modular Arithmetic
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Solution Overview
Problem
Fully Homomorphic Encryption (FHE) operations are significantly slower than plaintext operations due to heavy modular arithmetic computations on large vectors, making them 1,000 to 10,000 times slower.
Innovation Solution
A computer processing chip with an on-chip systolic array and AI accelerator that executes new instructions for multiplication, subtraction, and modular correction, while prefetching data to accelerate FHE operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If FHE operations are performed using traditional CPU-based computations, then security and encryption functionality are maintained, but computation speed deteriorates significantly (1,000 to 10,000 times slower than plaintext operations)
Solution Approach 1:
The FHE computation process is segmented into distinct operational phases (modular multiplication, modular addition, modular subtraction) that can be executed in parallel using a systolic array. This segmentation allows the system to process multiple elements simultaneously, dramatically improving computation speed and throughput compared to sequential CPU execution.
Solution Approach 2:
A specialized FHE instruction set acts as an intermediary layer between the CPU and the systolic array. This instruction set translates high-level FHE operations into optimized low-level operations that the systolic array can execute efficiently, bridging the gap between general-purpose computing and specialized hardware acceleration.
2Quantity of substance
If modular arithmetic computations are performed on large vectors (e.g., 65536 coefficients), then FHE functionality is maintained, but computation time increases significantly
Solution Approach 1:
The system transitions from one-dimensional sequential processing to two-dimensional parallel processing using the systolic array architecture. Multiple computation elements operate simultaneously on different portions of the large vector, effectively adding a spatial dimension to the computation and reducing overall processing time for large datasets.
Solution Approach 2:
Data is pre-loaded into the systolic array's on-chip memory before computation begins. This preliminary action eliminates the need for repeated memory accesses during computation, significantly reducing computation time for large vectors by keeping all necessary data readily available in fast on-chip storage.
3Adaptability or versatility
If polynomial vectors with 65536 coefficients are processed, then FHE operational capability is maintained, but processing speed deteriorates by 1,000 to 10,000 times
Solution Approach 1:
The systolic array is designed with a universal instruction set that can handle various FHE operations (multiplication, addition, subtraction, modular reduction) on polynomial vectors of different sizes. This multi-functionality maintains FHE operational capability while achieving high processing speeds through hardware acceleration.
Solution Approach 2:
The system dynamically adjusts computation parameters such as vector size, modulus, and operation type to optimize processing speed. By changing these parameters based on the specific FHE operation required, the system maintains full operational capability while achieving up to 10,000x speedup over traditional CPU execution.
Data Source
AI summary
Provided are techniques for accelerating a Fully Homomorphic Encryption (FHE) operation with an on-chip systolic array. A computer processing chip comprises an Artificial Intelligence (AI) accelerator comprising a direct memory access and a systolic array, a Level 3 (L3) cache connected to the AI accelerator, and a core connected to the AI accelerator and the L3 cache. The AI accelerator receives AI accelerator code from the core, where the AI accelerator code comprises new instructions, where the systolic array executes the new instructions using first data by executing a BMUL instruction to perform multiplication and generate first results, a BSUB instruction to perform subtraction using the first results to generate second results, and a BADDSUB instruction to perform modular correction on the second results to generate final results, and where the direct memory access prefetches second data for the systolic array.