Systolic Array Matrix Multiplication Circuit
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Solution Overview
Problem
Modern signal and image processing systems face challenges in efficiently performing matrix multiplication due to varying throughput requirements, which can be difficult to implement while optimizing system resources.
Innovation Solution
A matrix multiplication circuit comprising systolic arrays, pre-processing, and post-processing circuits that decompose input matrices into sub-matrices and perform optimal multiplication based on throughput requirements and matrix dimensions, allowing for flexible and resource-efficient matrix multiplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processing cells in systolic arrays is increased to achieve high-throughput matrix multiplication, then throughput is improved, but device complexity and resource usage increase
Solution Approach 1:
The patent divides the input matrices into multiple sub-matrices and uses multiple systolic arrays to process them in parallel. Each systolic array handles a specific subset of matrix multiplication operations, allowing the system to achieve high throughput without requiring a single large array with excessive processing cells. This segmentation distributes the computational load across multiple smaller units.
Solution Approach 2:
The patent implements a dynamic configuration system where the number of active systolic arrays and the size of sub-matrices can be adjusted based on the specific throughput requirements and matrix dimensions. This allows the system to adaptively configure processing resources, using more arrays for higher throughput applications while reducing complexity for lower throughput needs.
2Device complexity
If the size of systolic arrays is reduced to minimize resource usage, then device complexity is decreased, but throughput capability is reduced
Solution Approach 1:
The patent combines multiple systolic arrays into a unified processing system that operates in parallel. By merging the output of multiple smaller arrays through the post-processing circuit, the system achieves throughput equivalent to or greater than a single large array while using fewer processing cells total. The pre-processing circuit distributes input matrices to multiple systolic arrays simultaneously, enabling parallel computation.
3Adaptability or versatility
If matrix decomposition into sub-matrices is implemented to enable flexible throughput requirements, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent designs a universal matrix multiplication circuit where the pre-processing and post-processing circuits can handle various matrix dimensions and decomposition configurations. The same basic circuit structure can accommodate different numbers of systolic arrays and sub-matrix sizes depending on the application requirements, providing multi-functionality without requiring separate dedicated circuits for each configuration.
Data Source
AI summary
In one embodiment, a matrix multiplication circuit is provided. The circuit includes a plurality of systolic arrays, a pre-processing circuit, and a post-processing circuit. The pre-processing circuit is configured to receive first and second input matrices, and decompose the first input matrix into a plurality of sub-matrices. The pre-processing circuit inputs each of the plurality of sub-matrices to at least a respective one of the plurality of systolic arrays for multiplication with the second input matrix. The post-processing circuit is configured to combine output of the systolic arrays into a result matrix.