Systolic Array Processing Element for Mixed Integer and Floating-Point Operations
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Solution Overview
Problem
Systolic arrays supporting longer data types in artificial neural networks incur increased complexity, cost, and latency, while existing solutions complicate processing elements with specialized circuitry for asymmetric quantization, leading to inefficiencies in power consumption and hardware size.
Innovation Solution
The implementation of a systolic array that quantizes longer data types into shorter types, using partial de-quantization to simplify arithmetic logic and shared circuitry for both integer and floating-point operations, reducing the need for complex circuitry and specialized components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If systolic arrays support longer data types (e.g., 32-bit, 64-bit), then data type compatibility and precision are improved, but complexity, size, and cost of processing elements increase
Solution Approach 1:
The processing element is divided into multiple specialized units: an integer processing unit for integer operations and a floating-point processing unit for floating-point operations. Each unit is optimized for its specific data type, allowing the system to handle both integer and floating-point data types without requiring a single complex unit that supports all types simultaneously. This segmentation reduces the complexity of individual processing units while maintaining support for multiple data types.
2Adaptability or versatility
If systolic arrays support multiple data types with specialized circuitry, then data type compatibility is improved, but hardware size and power consumption increase
Solution Approach 1:
The processing element achieves multi-functionality by incorporating both integer and floating-point processing units within a single unified structure. This allows the same processing element to handle multiple data types (integers and floating-point numbers) without requiring separate dedicated hardware for each data type. The universal design reduces overall hardware size compared to having separate processing elements for each data type, while maintaining full compatibility with multiple data formats.
3Measurement precision
If systolic arrays use specialized circuitry for asymmetric quantization, then precision for specific data types is improved, but device complexity and power consumption increase
Solution Approach 1:
The processing element dynamically selects and activates only the circuitry needed for the current data type being processed. When handling integer data, the integer processing unit is activated; when handling floating-point data, the floating-point processing unit is activated. This dynamic activation reduces power consumption by avoiding the continuous operation of all specialized circuits, while still maintaining high precision for the specific data type being processed through the appropriate specialized unit.
Data Source
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AI summary
Systems and methods are provided to perform multiply-accumulate operations of multiple data types in a systolic array to increase clock speeds and/or reduce the size and quantity of systolic arrays required to perform multiply-accumulate operations of multiple data types. Each processing element in the systolic array can have a shared multiplier and one or more adders. The shared multiplier can have a separate and/or a shared circuitry where the shared circuitry is capable of performing at least a part of integer multiplication and at least a part of non-integer multiplication. The one or more adders can be a shared adder or separate adders. The shared adder can have a separate and a shared circuitry wherein the shared circuitry is capable of performing at least a part of integer addition and at least a part of non-integer addition.