Systolic Array Normalizer for Denormal Number Handling

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Solution Overview

Problem

Systolic arrays used in artificial neural networks face challenges in supporting both normal and denormal numbers, leading to increased complexity, size, and power consumption, which negatively impacts processing speed and user experience, especially during the inference phase.

Innovation Solution

Implementing a systolic array with a column of normalizers that normalize inputs, allowing for efficient representation of both normal and denormal numbers without requiring additional circuitry for each data type, using components like denormal detectors, exponent expanders, and multiplexers to convert inputs into a standardized format.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If computational support for denormal numbers is provided in the systolic array, then numerical underflow can be accommodated, but the complexity, size and cost of the processing elements increase

Engineering Contradiction:
Improvesupport for denormal numbersVSAvoidcomplexity of processing elements
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by normalizing denormal numbers before they enter the systolic array through a column of normalizers. This pre-processing converts denormal numbers to normalized form in advance, so the core processing elements don't need to handle denormal numbers directly, reducing their complexity while still supporting the full range of numeric values.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary structure (a column of normalizers) between the input and the processing elements. This intermediary layer handles the complexity of denormal number conversion separately, allowing the main processing elements to operate with simplified, normalized inputs only.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If computational support for denormal numbers is provided in the systolic array, then numerical underflow can be accommodated, but the size of the systolic array increases

Engineering Contradiction:
Improvesupport for denormal numbersVSAvoidsize of systolic array
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

By performing normalization in advance before the data enters the systolic array, the patent avoids the need to increase the size of the array itself to accommodate denormal number handling capabilities. The normalization column processes denormal numbers externally.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The intermediary normalization column handles the size-increasing requirements externally, allowing the main systolic array to maintain a compact size optimized for normalized number processing while still supporting denormal inputs through the normalization layer.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If computational support for denormal numbers is provided in the systolic array, then numerical underflow can be accommodated, but power consumption increases

Engineering Contradiction:
Improvesupport for denormal numbersVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent performs the energy-intensive normalization operation in advance, before the data enters the systolic array. This allows the main processing elements to operate more efficiently with normalized numbers, reducing overall power consumption while still supporting denormal inputs.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The intermediary normalization column handles the power-consuming denormal number conversion separately, allowing the main systolic array to operate with lower power consumption by processing only normalized numbers.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Reliability

If computational support for denormal numbers is provided in the systolic array, then numerical underflow can be accommodated, but processing speed decreases

Engineering Contradiction:
Improvesupport for denormal numbersVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By normalizing denormal numbers in advance before they enter the systolic array, the patent eliminates the processing delays that would occur if the array had to handle denormal numbers during computation. This pre-processing approach maintains faster processing speeds.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The intermediary normalization column handles denormal number conversion externally, allowing the main systolic array to operate at optimal speed for normalized number processing while still supporting denormal inputs through the pre-processing layer.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240361986A1Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range
Publication Date: 2024.10.31 AMAZON TECH INC
  • US20240361986A1 patent drawing
  • US20240361986A1 patent drawing
  • US20240361986A1 patent drawing

AI summary

Systems and methods are provided to perform multiply-accumulate operations of at least one normalized number in a systolic array. The systolic array can obtain a first input and detect that the first input is denormal. Based on determining the first input is denormal, the systolic array can generate a first normalized number by normalizing the first input. Processing elements of the systolic array can include a multiplier and an adder. The multiplier can multiply the first normalized number by a second normal or normalized number to generate a multiplier product and the adder can add an input partial sum to the multiplier product to generate an addition result.