Systolic Array Reducer for Arbitrary Bit-Length Input Processing
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Solution Overview
Problem
Traditional systolic arrays face challenges in supporting arbitrary bit-length inputs efficiently, leading to increased power consumption and complexity, which negatively impacts processing speed and user experience, especially when handling longer bit-lengths like 32-bit floating-point numbers.
Innovation Solution
The systolic array employs a reducer to convert inputs of arbitrary bit-length into reduced inputs, allowing for single-pass reduced precision computations, thereby supporting arbitrary bit-lengths with minimal loss in efficiency for shorter bit-lengths, using multiple reduced inputs for multiple-pass full precision computations to maintain accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the systolic array supports arbitrary bit-length inputs directly, then the precision and accuracy of computations are improved, but the device complexity and power consumption increase significantly
Solution Approach 1:
The patent segments the input data processing into two distinct stages: a reduction stage that converts arbitrary bit-length inputs into fixed bit-length reduced inputs, and a computation stage that processes these reduced inputs through the systolic array. This segmentation allows the array to maintain fixed complexity while still supporting arbitrary precision inputs through the intermediary reduction process.
Solution Approach 2:
The patent introduces a reduction mechanism as an intermediary component that sits between the arbitrary precision input and the fixed precision systolic array. This intermediary converts high-precision inputs into reduced-precision representations that the array can process efficiently, thereby enabling arbitrary bit-length support without increasing the array's inherent complexity.
2Measurement precision
If the systolic array supports 32-bit floating-point numbers, then the accuracy for mathematical operations is improved, but the processing speed decreases
Solution Approach 1:
The patent performs preliminary reduction of 32-bit floating-point inputs into fixed bit-length reduced inputs before they enter the systolic array. This preliminary action prepares the data in a format that the array can process at full speed, thereby maintaining high processing speed while still supporting accurate 32-bit computations through the reduction process.
Solution Approach 2:
The patent changes the bit-length parameter of the input data from arbitrary (including 32-bit) to a fixed reduced bit-length through the reduction mechanism. This parameter transformation allows the systolic array to operate at its native optimal speed while still representing and processing the original higher-precision values through the reduced format.
3Power
If the systolic array is designed to handle increased bit-lengths, then the computational power is improved, but the system size and cost increase
Solution Approach 1:
The patent makes the systolic array universal by enabling it to process arbitrary bit-length inputs through the reduction mechanism. The same fixed-size array can handle various input precisions (16-bit, 32-bit, or other bit-lengths) by converting them all to the array's native fixed bit-length format, thereby achieving multi-functionality without increasing the array's physical size.
Solution Approach 2:
The patent creates a reduced copy of the arbitrary precision input data that fits within the fixed bit-length constraints of the systolic array. This reduced copy retains the essential computational information needed for the computation while using fewer bits, allowing the array to process high-precision data without requiring physical hardware proportional to the input bit-length.
4Adaptability or versatility
If the systolic array processes arbitrary bit-length inputs with fixed precision elements, then the adaptability is improved, but the power consumption increases
Solution Approach 1:
The patent segments the processing into a reduction phase and a computation phase. The reduction phase handles the adaptability requirement by converting arbitrary bit-length inputs to fixed formats, while the computation phase uses the fixed-precision systolic array operating at its optimal power efficiency. This segmentation allows adaptability without sustaining high power consumption throughout the entire processing pipeline.
Data Source
AI summary
Systems and methods are provided to perform multiply-accumulate operations of reduced precision numbers in a systolic array. Each row of the systolic array can receive reduced inputs from a respective reducer. The reduced input can include a reduced input data element and/or a reduced weight. The systolic array may lack support for inputs with a first bit-length and the reducers may reduce the bit-length of a given input from the first bit-length to a second shorter bit-length and provide the reduced input to the array. In order to reduce the bit-length, the reducer may reduce the number of trailing bits of the input. Further, the systolic array can receive a reduced and rounded input. The systolic array can propagate the reduced input through the processing elements in the systolic array. Each processing element may include a multiplier and/or an adder to perform arithmetical operations based on the reduced input.