Systolic Array Split-Term Matrix Multiplication for Single Precision
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Solution Overview
Problem
Current graphics processing units (GPUs) face limitations in efficiently processing graphics and machine-learning operations due to the need for specialized hardware and complex scheduling algorithms, which can lead to suboptimal performance and resource utilization.
Innovation Solution
A GPU architecture with a parallel processing unit that includes a scheduler for distributing workloads across processing clusters, utilizing SIMT architecture and systolic array hardware to support single precision operations, enabling efficient execution of graphics and machine-learning tasks through optimized thread execution and data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If specialized hardware and complex scheduling algorithms are used for graphics processing, then processing capability for graphics operations is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal processing architecture where a single set of processing units can execute both graphics operations and machine learning workloads. The system uses a unified instruction set and processing clusters that can be dynamically configured for different task types, eliminating the need for separate specialized hardware for graphics and ML functions while maintaining high performance for both domains.
Solution Approach 2:
The system employs dynamic workload distribution where processing clusters can be dynamically allocated and reassigned based on the current task requirements. The scheduler dynamically partitions workloads between graphics processing clusters and machine learning processing clusters, allowing the system to adapt to varying computational demands without requiring static specialized hardware for each function.
2Reliability
If specialized hardware and complex scheduling algorithms are used for machine learning operations, then processing capability for ML tasks is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal processing architecture where a single set of processing units can execute both graphics operations and machine learning workloads. The system uses a unified instruction set and processing clusters that can be dynamically configured for different task types, eliminating the need for separate specialized hardware for graphics and ML functions while maintaining high performance for both domains.
Solution Approach 2:
The system divides the processing architecture into distinct processing clusters - graphics processing clusters and machine learning processing clusters - that can operate independently but share common resources. This segmentation allows specialized computation patterns for ML tasks to be implemented through software configuration rather than dedicated hardware, reducing overall device complexity while maintaining ML processing capability.
3Productivity
If parallel processing is maximized to improve performance, then productivity is improved, but computational overhead increases
Solution Approach 1:
The system divides workloads into discrete units that can be independently distributed to processing clusters. Each processing cluster handles specific portions of the computational graph, allowing parallel execution without requiring complex coordination overhead. The segmentation of tasks enables simple, efficient distribution while maintaining high parallelism and productivity.
Data Source
AI summary
An apparatus to facilitate single precision support for systolic pipeline in a graphics environment is disclosed. The apparatus includes a processor comprising systolic array hardware including a plurality of data processing units, wherein the systolic array hardware is to: receive data for performance of a matrix multiplication operation in a first precision format; convert an original value of the data into two split values with a second precision format having a lower precision than the first precision format; perform the matrix multiplication operation using the two split values in the second precision format, the matrix multiplication operation comprising a split-term operation that utilizes two passes through the systolic array hardware with feedback wiring and local reduction; and generate an emulated result for the matrix multiplication operation in the first precision format.