Systolic Array On-Array Sorting and Convolution
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Solution Overview
Problem
Existing systolic arrays lack a sorting computation function, leading to inefficient utilization and increased bandwidth waste due to the need for data transfer to external apparatuses for sorting operations, which is not directly supported within the array.
Innovation Solution
Incorporating a systolic array with basic computation units that include feature input registers, result buffers, comparators, and control registers, allowing for on-array sorting and convolution operations, thereby eliminating the need for external data transfer and enhancing utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data is transferred to external apparatuses for sorting operations, then sorting functionality is achieved, but bandwidth is wasted and computation time increases
Solution Approach 1:
The patent merges the sorting function directly into the systolic array by integrating comparators and control logic within the existing computational units. This allows sorting operations to be performed concurrently with data flow through the array, eliminating the need for separate external sorting apparatuses and reducing bandwidth waste.
Solution Approach 2:
The systolic array is designed to perform multiple functions including both computational operations and sorting operations. By making the systolic array universal, it can handle different data processing tasks without requiring external specialized hardware, thereby improving resource utilization and reducing bandwidth consumption.
2Productivity
If additional heap sort hardware unit is added, then sorting operator is efficiently processed, but unnecessary area is increased
Solution Approach 1:
Instead of adding separate heap sort hardware units, the patent combines sorting functionality with the existing systolic array structure. The comparators and control registers are integrated into the same physical space as the computational units, achieving sorting efficiency without increasing overall hardware area.
Solution Approach 2:
The systolic array units are designed to perform both computational tasks and sorting tasks. This multi-functionality allows the same hardware area to serve dual purposes, eliminating the need for additional dedicated sorting hardware and thus avoiding area increase.
3Adaptability or versatility
If data is transferred from systolic array to external units, then sorting can be performed, but utilization rate of systolic array decreases
Solution Approach 1:
The sorting capability is merged directly into the systolic array architecture, allowing data to be sorted in-place as it flows through the array. This eliminates data transfer to external units and keeps the systolic array continuously utilized for both computation and sorting operations.
Solution Approach 2:
The systolic array maintains continuous useful action by performing sorting operations concurrently with data flow. Data is sorted in-place during its traversal through the array, ensuring that the array remains fully utilized without idle periods caused by data transfer to external sorting units.
4Adaptability or versatility
If sorting operation is performed externally, then sorting is achieved, but computation time increases
Solution Approach 1:
Sorting operation is merged with the data flow through the systolic array, allowing sorting to occur concurrently with computation. This parallel execution eliminates sequential overhead and reduces total computation time compared to external sorting operations.
Solution Approach 2:
The sorting operation is performed preliminarily as data flows through the systolic array, preparing data for subsequent operations without requiring additional processing time. By sorting in-place during data traversal, the system avoids post-computation sorting delays.
Data Source
AI summary
A systolic array includes a plurality of basic computation units arranged in a matrix. A basic computation includes a feature input register configured to store first feature data, a result buffer configured to store first temporary data, a comparator connected to the feature input register and the result buffer, and a control register connected to the feature input register, the result buffer, and the comparator. The comparator is configured to compare the first feature data input with the first temporary data successively. The control register is configured to control the first feature data of the feature input register and the first temporary data to be input to the comparator, output a comparison result to the result buffer and a feature input register of a next basic computation unit, and after sorting, output the first temporary data last stored in the result buffer as a first data result.