2D Systolic Array Hardware Accelerator for Sparse CNN Data Manipulation
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Solution Overview
Problem
Convolutional neural networks (CNNs) are challenging to implement in constrained devices due to the high number of MAC operations required, which are computationally intensive and power-consuming, especially when dealing with large data structures and sparse data, where existing methods struggle to effectively exploit sparsity for power reduction and throughput enhancement.
Innovation Solution
A hardware accelerator is designed to exploit operand sparsity by using a 2D systolic array architecture that eliminates the need for indexed data representation, leveraging 1-bit signals to clock gate data registers and exposing more operands to each MAC element, thereby increasing hardware utilization and throughput while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional CNN implementation methods are used on constrained devices, then computational accuracy is maintained, but power consumption is excessively high and throughput is low
Solution Approach 1:
The patent extracts and eliminates redundant MAC operations by exploiting operand sparsity. It identifies and removes operations involving zero operands from the computational workflow, thereby reducing the total number of operations executed on constrained devices while maintaining computational accuracy for non-zero elements.
Solution Approach 2:
The patent implements dynamic operation scheduling based on operand sparsity patterns. The system adaptively adjusts the number and timing of MAC operations executed by the DSP based on the actual sparsity of input data, allowing the computational workload to vary dynamically rather than executing a fixed sequence of operations.
2Use of energy by moving object
If sparsity exploitation methods are implemented, then power consumption is reduced, but computational accuracy may be compromised
Solution Approach 1:
The patent selectively extracts only the zero operands from the computational process, leaving all non-zero operands to be processed with full precision. This extraction approach ensures that computational accuracy is maintained for all meaningful data elements while eliminating waste on zero values.
Solution Approach 2:
The system incorporates feedback mechanisms that monitor the sparsity patterns of input data and adjust the computational workflow accordingly. The DSP receives feedback about which operands are zero and dynamically modifies its operation schedule to maintain accuracy for non-zero elements while skipping zero operations.
3Productivity
If more MAC operations are executed to handle large data structures, then computational completeness is achieved, but hardware resource utilization is inefficient
Solution Approach 1:
The patent applies partial action by executing only the necessary subset of MAC operations required for non-zero operands. Instead of performing complete operations on all data elements including zeros, the system performs partial computation only where needed, improving hardware utilization efficiency.
Solution Approach 2:
The system changes the operational parameters of the DSP based on data sparsity characteristics. It dynamically adjusts the number of MAC operations, the size of data structures processed, and the timing of operations to match the actual computational requirements, thereby improving hardware resource utilization.
Data Source
AI summary
A system, apparatus and method for exposing input data operands and input weight operands to elements of a two-dimensional array so that two pairs of operands are exposed to each element of the array.