High-Level Synthesis for Systolic Array Generation on FPGAs
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Solution Overview
Problem
Designing systolic arrays on target devices like FPGAs is challenging due to the need for extensive knowledge in both algorithmic and hardware aspects, and the difficulty in tuning performance using hardware description languages, which is time-consuming and requires expertise.
Innovation Solution
A method and apparatus for generating systolic arrays using a high-level synthesis language, such as OpenCL, that allows users to input information about the array, generating descriptions of processing elements, channels, data transmitters, and receivers, and performing optimizations like external channel fan-out minimization, data buffering, and latency reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If hardware description language is used to design systolic arrays, then implementation precision is improved, but design complexity and time consumption increase
Solution Approach 1:
The patent introduces an intermediary tool that translates high-level algorithmic descriptions into hardware description language. This intermediary automatically generates the complex HDL code needed for precise FPGA implementation, eliminating the need for designers to manually write complex HDL while maintaining implementation precision.
Solution Approach 2:
The patent replaces the manual mechanical process of writing and tuning HDL code with an automated computational system. The tool automatically generates and optimizes HDL code from high-level specifications, substituting the time-consuming manual HDL development process with automated code generation.
2Productivity
If hardware description language is used to tune performance, then performance optimization is improved, but time consumption increases
Solution Approach 1:
The patent performs preliminary optimization actions by automatically analyzing the algorithmic description and pre-optimizing the generated HDL code before implementation. The tool incorporates optimization strategies during the code generation phase, eliminating the need for time-consuming iterative manual tuning.
Solution Approach 2:
The patent enables the design system to self-optimize by automatically analyzing performance requirements and generating optimized HDL code without human intervention. The tool performs self-service optimization by selecting appropriate optimization strategies and applying them automatically during code generation.
3Manufacturing precision
If extensive knowledge in algorithm and hardware acceleration is required, then design quality is improved, but ease of operation deteriorates
Solution Approach 1:
The patent introduces an intermediary translation tool that bridges the gap between algorithmic descriptions and hardware implementation. This intermediary handles the complex knowledge requirements internally, allowing users with algorithmic expertise to design systolic arrays without needing deep hardware description language knowledge.
Data Source
AI summary
A method for generating a description of a systolic array includes prompting a user to input information about the systolic array. A high-level synthesis language is generated that describes channels of processing elements of the systolic array and a topology of the processing elements in response to the information provided by the user.