Systolic Array Zero Copy Message Passing
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Solution Overview
Problem
The overhead of message passing in systolic arrays, particularly due to interactions with DMA engines or message passing interfaces, burdens the processor and reduces cycles available for other work, leading to performance delays in highly optimized pipelines.
Innovation Solution
A zero copy pipeline mechanism where the Receive Queue (RQ) and Send Queue (SQ) share the same queue memory location, eliminating the need for message copying and minimizing processor interaction with hardware, with the hardware automatically managing indices and data transfer operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If message passing is implemented using separate RQ and SQ with traditional hardware interaction, then message transmission functionality is achieved, but processor overhead increases and available cycles for other work decreases
Solution Approach 1:
The patent combines the Receive Queue (RQ) and Send Queue (SQ) into a single shared queue memory structure with the same base address and entry size. This merging eliminates the need for separate hardware interactions for receiving and sending messages, reducing processor overhead and freeing up processor cycles for other computational tasks while maintaining full message passing functionality.
2Productivity
If traditional separate queue implementation is used, then message passing is supported, but performance is reduced due to copying overhead between queues
Solution Approach 1:
By implementing RQ and SQ as the same queue structure in shared memory with identical base addresses and entry sizes, the patent eliminates the data copying operation between separate queues. Messages are directly accessible from the same memory location, removing the time penalty associated with memory copy operations and significantly improving pipeline performance.
Solution Approach 2:
The patent applies a zero-copy approach where the message data is not copied from RQ to SQ. Instead, the same queue memory location serves both receive and send operations, eliminating the redundant copying step that traditionally caused performance delays in message passing pipelines.
3Ease of manufacture
If RQ and SQ are placed in the same memory location with same base address, then message copying is eliminated, but queue management complexity increases
Solution Approach 1:
The patent merges RQ and SQ into a single queue structure with the same base address, entry size, and number of entries. This unified structure simplifies the overall implementation by eliminating the need for separate queue management logic, reducing the complexity of message passing implementation despite the shared memory arrangement.
Data Source
AI summary
The present subject disclosure presents a hardware mechanism and usage model for using a compute element of a systolic array to handle messages from an RQ (Receive Queue) to SQ (Send Queue) without requiring a copy between queues and also minimizing the local processor's interaction with the send and receive queue hardware.