Systolic Array Zero Detection for Dynamic Power Reduction

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Solution Overview

Problem

Systolic arrays used in neural networks face significant dynamic power consumption due to concurrent multiply-accumulate operations, especially when dealing with zero values and no-operation cycles, which waste energy and increase heat dissipation.

Innovation Solution

Implementing zero detector circuits external to processing elements (PEs) to identify zero input data and weight values, allowing for the skipping of multiplication operations and reducing power consumption by using zero indicators to gate registers and bypass multiplication results.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If zero detector circuits are implemented external to processing elements, then dynamic power consumption is reduced by skipping unnecessary multiplication operations, but device complexity increases due to additional detection circuitry and control mechanisms

Engineering Contradiction:
Improvedynamic power consumptionVSAvoiddevice complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The zero detector circuits are extracted from within each processing element and placed externally, allowing individual PEs to skip multiplication operations when input data or weights are zero. This extraction reduces the computational workload and power consumption of each PE while centralizing the detection function.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Zero detection is performed before multiplication operations to identify cases where computation can be skipped. By detecting zero values in advance and generating skip signals, the system avoids performing unnecessary arithmetic operations, thereby reducing dynamic power consumption.

Inventive Principle:
Principle #10Preliminary action

2Use of energy by moving object

If multiplication operations are skipped for zero values, then energy efficiency is improved, but manufacturing precision may be affected due to approximate computation

Engineering Contradiction:
Improveenergy efficiencyVSAvoidcomputation precision
Core Design Contradiction:
Use of energy by moving objectVSManufacturing precision

Solution Approach 1:

The patent implements a skip mechanism that bypasses multiplication operations when the input data element or weight is zero. The zero detector circuits identify zero values and generate skip signals that prevent unnecessary computation, directly improving energy efficiency by eliminating wasted arithmetic operations on zero operands.

Inventive Principle:
Principle #21Skipping (Rushing through)

Data Source

PatentUS10817260B1Reducing dynamic power consumption in arrays
Publication Date: 2020.10.27 AMAZON TECH INC
  • US10817260B1 patent drawing
  • US10817260B1 patent drawing
  • US10817260B1 patent drawing

AI summary

Systems and methods are provided to skip multiplication operations with zeros in processing elements of the systolic array to reduce dynamic power consumption. A value of zero can be detected on an input data element entering each row of the array and respective zero indicators may be generated. These respective zero indicators may be passed to all the processing elements in the respective rows. The multiplication operation with the zero value can be skipped in each processing element based on the zero indicators, thus reducing dynamic power consumption.